Lines Matching refs:fw_shared
196 volatile struct amdgpu_fw_shared *fw_shared; in vcn_v3_0_sw_init() local
276 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; in vcn_v3_0_sw_init()
277 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | in vcn_v3_0_sw_init()
280 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); in vcn_v3_0_sw_init()
281 fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG; in vcn_v3_0_sw_init()
283 fw_shared->smu_interface_info.smu_interface_type = 2; in vcn_v3_0_sw_init()
286 fw_shared->smu_interface_info.smu_interface_type = 1; in vcn_v3_0_sw_init()
337 volatile struct amdgpu_fw_shared *fw_shared; in vcn_v3_0_sw_fini() local
341 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; in vcn_v3_0_sw_fini()
342 fw_shared->present_flag_0 = 0; in vcn_v3_0_sw_fini()
343 fw_shared->sw_ring.is_enabled = false; in vcn_v3_0_sw_fini()
574 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v3_0_mc_resume()
576 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v3_0_mc_resume()
666 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
669 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1042 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v3_0_start_dpg_mode() local
1154 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); in vcn_v3_0_start_dpg_mode()
1179 fw_shared->rb.rptr = 0; in vcn_v3_0_start_dpg_mode()
1180 fw_shared->rb.wptr = lower_32_bits(ring->wptr); in vcn_v3_0_start_dpg_mode()
1183 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); in vcn_v3_0_start_dpg_mode()
1201 volatile struct amdgpu_fw_shared *fw_shared; in vcn_v3_0_start() local
1341 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; in vcn_v3_0_start()
1342 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); in vcn_v3_0_start()
1357 fw_shared->rb.wptr = lower_32_bits(ring->wptr); in vcn_v3_0_start()
1358 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); in vcn_v3_0_start()
1362 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); in vcn_v3_0_start()
1369 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); in vcn_v3_0_start()
1371 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); in vcn_v3_0_start()
1378 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); in vcn_v3_0_start()
1722 volatile struct amdgpu_fw_shared *fw_shared; in vcn_v3_0_pause_dpg_mode() local
1756 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v3_0_pause_dpg_mode()
1757 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); in vcn_v3_0_pause_dpg_mode()
1765 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); in vcn_v3_0_pause_dpg_mode()
1767 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); in vcn_v3_0_pause_dpg_mode()
1775 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); in vcn_v3_0_pause_dpg_mode()
1778 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); in vcn_v3_0_pause_dpg_mode()
1779 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); in vcn_v3_0_pause_dpg_mode()
1841 volatile struct amdgpu_fw_shared *fw_shared; in vcn_v3_0_dec_ring_set_wptr() local
1845 fw_shared = adev->vcn.inst[ring->me].fw_shared.cpu_addr; in vcn_v3_0_dec_ring_set_wptr()
1846 fw_shared->rb.wptr = lower_32_bits(ring->wptr); in vcn_v3_0_dec_ring_set_wptr()