Lines Matching refs:indirect
522 bool indirect) in vcn_v4_0_mc_resume_dpg_mode() argument
533 if (!indirect) { in vcn_v4_0_mc_resume_dpg_mode()
536 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
539 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
541 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
544 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
546 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
548 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
554 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
557 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
561 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
564 if (!indirect) in vcn_v4_0_mc_resume_dpg_mode()
566 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
569 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
572 if (!indirect) { in vcn_v4_0_mc_resume_dpg_mode()
575 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
578 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
580 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
583 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
585 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
587 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
590 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
595 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
598 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
600 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
602 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
607 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
610 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
612 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
615 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
620 adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
868 uint8_t indirect) in vcn_v4_0_disable_clock_gating_dpg_mode() argument
901 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
905 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
909 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
913 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
977 bool indirect) in vcn_v4_0_enable_ras() argument
992 tmp, 0, indirect); in vcn_v4_0_enable_ras()
997 tmp, 0, indirect); in vcn_v4_0_enable_ras()
1008 static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) in vcn_v4_0_start_dpg_mode() argument
1025 if (indirect) in vcn_v4_0_start_dpg_mode()
1029 vcn_v4_0_disable_clock_gating_dpg_mode(vinst, 0, indirect); in vcn_v4_0_start_dpg_mode()
1035 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_start_dpg_mode()
1039 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); in vcn_v4_0_start_dpg_mode()
1051 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v4_0_start_dpg_mode()
1055 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); in vcn_v4_0_start_dpg_mode()
1062 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v4_0_start_dpg_mode()
1069 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v4_0_start_dpg_mode()
1075 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v4_0_start_dpg_mode()
1077 vcn_v4_0_mc_resume_dpg_mode(vinst, indirect); in vcn_v4_0_start_dpg_mode()
1082 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_start_dpg_mode()
1087 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); in vcn_v4_0_start_dpg_mode()
1089 vcn_v4_0_enable_ras(vinst, indirect); in vcn_v4_0_start_dpg_mode()
1094 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); in vcn_v4_0_start_dpg_mode()
1097 if (indirect) in vcn_v4_0_start_dpg_mode()