Lines Matching refs:rb_setup
1364 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; in vcn_v4_0_start_sriov() local
1456 rb_setup = &fw_shared->rb_setup; in vcn_v4_0_start_sriov()
1462 rb_setup->is_rb_enabled_flags |= RB_ENABLED; in vcn_v4_0_start_sriov()
1468 …memset((void *)&rb_setup->rb_info, 0, sizeof(struct amdgpu_vcn_rb_setup_info) * MAX_NUM_VCN_RB_SET… in vcn_v4_0_start_sriov()
1470 rb_setup->rb_info[0].rb_addr_lo = lower_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr); in vcn_v4_0_start_sriov()
1471 rb_setup->rb_info[0].rb_addr_hi = upper_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr); in vcn_v4_0_start_sriov()
1472 rb_setup->rb_info[0].rb_size = adev->vcn.inst[0].ring_enc[0].ring_size / 4; in vcn_v4_0_start_sriov()
1475 rb_setup->rb_info[2].rb_addr_lo = lower_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr); in vcn_v4_0_start_sriov()
1476 rb_setup->rb_info[2].rb_addr_hi = upper_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr); in vcn_v4_0_start_sriov()
1477 rb_setup->rb_info[2].rb_size = adev->vcn.inst[1].ring_enc[0].ring_size / 4; in vcn_v4_0_start_sriov()
1482 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); in vcn_v4_0_start_sriov()
1483 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); in vcn_v4_0_start_sriov()
1484 rb_setup->rb_size = ring_enc->ring_size / 4; in vcn_v4_0_start_sriov()