Lines Matching refs:indirect
99 int inst_idx, bool indirect);
532 bool indirect) in vcn_v4_0_3_mc_resume_dpg_mode() argument
544 if (!indirect) { in vcn_v4_0_3_mc_resume_dpg_mode()
548 inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
552 inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
554 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
557 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
559 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
561 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
567 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
570 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
574 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
577 if (!indirect) in vcn_v4_0_3_mc_resume_dpg_mode()
579 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
582 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
585 if (!indirect) { in vcn_v4_0_3_mc_resume_dpg_mode()
588 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
591 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
593 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
596 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
598 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
600 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
603 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
609 AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
613 AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
615 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
617 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
622 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
625 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
627 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
630 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
634 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
636 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
744 uint8_t indirect) in vcn_v4_0_3_disable_clock_gating_dpg_mode() argument
771 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
775 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
779 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
783 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
847 bool indirect) in vcn_v4_0_3_start_dpg_mode() argument
867 if (indirect) { in vcn_v4_0_3_start_dpg_mode()
878 vcn_v4_0_3_disable_clock_gating_dpg_mode(vinst, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
886 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
890 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
902 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
906 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
913 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v4_0_3_start_dpg_mode()
920 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v4_0_3_start_dpg_mode()
926 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v4_0_3_start_dpg_mode()
928 vcn_v4_0_3_mc_resume_dpg_mode(vinst, indirect); in vcn_v4_0_3_start_dpg_mode()
933 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
938 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
940 vcn_v4_0_3_enable_ras(adev, inst_idx, indirect); in vcn_v4_0_3_start_dpg_mode()
945 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
947 if (indirect) in vcn_v4_0_3_start_dpg_mode()
2166 int inst_idx, bool indirect) in vcn_v4_0_3_enable_ras() argument
2179 tmp, 0, indirect); in vcn_v4_0_3_enable_ras()
2184 tmp, 0, indirect); in vcn_v4_0_3_enable_ras()
2189 tmp, 0, indirect); in vcn_v4_0_3_enable_ras()