Lines Matching refs:adev
257 static int vi_query_video_codecs(struct amdgpu_device *adev, bool encode, in vi_query_video_codecs() argument
260 switch (adev->asic_type) { in vi_query_video_codecs()
298 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) in vi_pcie_rreg() argument
303 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
307 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
311 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_pcie_wreg() argument
315 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
320 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
323 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) in vi_smc_rreg() argument
328 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_smc_rreg()
331 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_smc_rreg()
335 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_smc_wreg() argument
339 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_smc_wreg()
342 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_smc_wreg()
349 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg) in cz_smc_rreg() argument
354 spin_lock_irqsave(&adev->smc_idx_lock, flags); in cz_smc_rreg()
357 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in cz_smc_rreg()
361 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in cz_smc_wreg() argument
365 spin_lock_irqsave(&adev->smc_idx_lock, flags); in cz_smc_wreg()
368 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in cz_smc_wreg()
371 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) in vi_uvd_ctx_rreg() argument
376 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_rreg()
379 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_rreg()
383 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_uvd_ctx_wreg() argument
387 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_wreg()
390 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_wreg()
393 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) in vi_didt_rreg() argument
398 spin_lock_irqsave(&adev->didt_idx_lock, flags); in vi_didt_rreg()
401 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in vi_didt_rreg()
405 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_didt_wreg() argument
409 spin_lock_irqsave(&adev->didt_idx_lock, flags); in vi_didt_wreg()
412 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in vi_didt_wreg()
415 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) in vi_gc_cac_rreg() argument
420 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_rreg()
423 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_rreg()
427 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_gc_cac_wreg() argument
431 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_wreg()
434 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_wreg()
485 static void vi_init_golden_registers(struct amdgpu_device *adev) in vi_init_golden_registers() argument
488 mutex_lock(&adev->grbm_idx_mutex); in vi_init_golden_registers()
490 if (amdgpu_sriov_vf(adev)) { in vi_init_golden_registers()
491 xgpu_vi_init_golden_registers(adev); in vi_init_golden_registers()
492 mutex_unlock(&adev->grbm_idx_mutex); in vi_init_golden_registers()
496 switch (adev->asic_type) { in vi_init_golden_registers()
498 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
503 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
508 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
513 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
518 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
529 mutex_unlock(&adev->grbm_idx_mutex); in vi_init_golden_registers()
540 static u32 vi_get_xclk(struct amdgpu_device *adev) in vi_get_xclk() argument
542 u32 reference_clock = adev->clock.spll.reference_freq; in vi_get_xclk()
545 if (adev->flags & AMD_IS_APU) { in vi_get_xclk()
546 switch (adev->asic_type) { in vi_get_xclk()
579 void vi_srbm_select(struct amdgpu_device *adev, in vi_srbm_select() argument
590 static bool vi_read_disabled_bios(struct amdgpu_device *adev) in vi_read_disabled_bios() argument
600 if (adev->mode_info.num_crtc) { in vi_read_disabled_bios()
609 if (adev->mode_info.num_crtc) { in vi_read_disabled_bios()
622 r = amdgpu_read_bios(adev); in vi_read_disabled_bios()
626 if (adev->mode_info.num_crtc) { in vi_read_disabled_bios()
635 static bool vi_read_bios_from_rom(struct amdgpu_device *adev, in vi_read_bios_from_rom() argument
647 if (adev->flags & AMD_IS_APU) in vi_read_bios_from_rom()
653 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_read_bios_from_rom()
661 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_read_bios_from_rom()
745 static uint32_t vi_get_register_value(struct amdgpu_device *adev, in vi_get_register_value() argument
756 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; in vi_get_register_value()
758 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; in vi_get_register_value()
760 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; in vi_get_register_value()
762 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1; in vi_get_register_value()
765 mutex_lock(&adev->grbm_idx_mutex); in vi_get_register_value()
767 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in vi_get_register_value()
772 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in vi_get_register_value()
773 mutex_unlock(&adev->grbm_idx_mutex); in vi_get_register_value()
780 return adev->gfx.config.gb_addr_config; in vi_get_register_value()
782 return adev->gfx.config.mc_arb_ramcfg; in vi_get_register_value()
816 return adev->gfx.config.tile_mode_array[idx]; in vi_get_register_value()
834 return adev->gfx.config.macrotile_mode_array[idx]; in vi_get_register_value()
841 static int vi_read_register(struct amdgpu_device *adev, u32 se_num, in vi_read_register() argument
853 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
869 static int vi_asic_pci_config_reset(struct amdgpu_device *adev) in vi_asic_pci_config_reset() argument
874 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in vi_asic_pci_config_reset()
877 pci_clear_master(adev->pdev); in vi_asic_pci_config_reset()
879 amdgpu_device_pci_config_reset(adev); in vi_asic_pci_config_reset()
884 for (i = 0; i < adev->usec_timeout; i++) { in vi_asic_pci_config_reset()
887 pci_set_master(adev->pdev); in vi_asic_pci_config_reset()
888 adev->has_hw_reset = true; in vi_asic_pci_config_reset()
895 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in vi_asic_pci_config_reset()
900 static int vi_asic_supports_baco(struct amdgpu_device *adev) in vi_asic_supports_baco() argument
902 switch (adev->asic_type) { in vi_asic_supports_baco()
909 return amdgpu_dpm_is_baco_supported(adev); in vi_asic_supports_baco()
916 vi_asic_reset_method(struct amdgpu_device *adev) in vi_asic_reset_method() argument
925 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in vi_asic_reset_method()
928 switch (adev->asic_type) { in vi_asic_reset_method()
935 baco_reset = amdgpu_dpm_is_baco_supported(adev); in vi_asic_reset_method()
957 static int vi_asic_reset(struct amdgpu_device *adev) in vi_asic_reset() argument
962 if (adev->flags & AMD_IS_APU) in vi_asic_reset()
965 if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { in vi_asic_reset()
966 dev_info(adev->dev, "BACO reset\n"); in vi_asic_reset()
967 r = amdgpu_dpm_baco_reset(adev); in vi_asic_reset()
969 dev_info(adev->dev, "PCI CONFIG reset\n"); in vi_asic_reset()
970 r = vi_asic_pci_config_reset(adev); in vi_asic_reset()
976 static u32 vi_get_config_memsize(struct amdgpu_device *adev) in vi_get_config_memsize() argument
981 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, in vi_set_uvd_clock() argument
988 r = amdgpu_atombios_get_clock_dividers(adev, in vi_set_uvd_clock()
996 if (adev->flags & AMD_IS_APU) in vi_set_uvd_clock()
1006 if (adev->flags & AMD_IS_APU) { in vi_set_uvd_clock()
1027 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in vi_set_uvd_clocks() argument
1031 if (adev->flags & AMD_IS_APU) { in vi_set_uvd_clocks()
1032 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS); in vi_set_uvd_clocks()
1036 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS); in vi_set_uvd_clocks()
1040 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); in vi_set_uvd_clocks()
1044 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); in vi_set_uvd_clocks()
1052 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in vi_set_vce_clocks() argument
1062 if (adev->flags & AMD_IS_APU) { in vi_set_vce_clocks()
1074 r = amdgpu_atombios_get_clock_dividers(adev, in vi_set_vce_clocks()
1106 static void vi_enable_aspm(struct amdgpu_device *adev) in vi_enable_aspm() argument
1121 static void vi_program_aspm(struct amdgpu_device *adev) in vi_program_aspm() argument
1127 if (!amdgpu_device_should_use_aspm(adev)) in vi_program_aspm()
1130 if (adev->asic_type < CHIP_POLARIS10) in vi_program_aspm()
1158 pci_read_config_dword(adev->pdev, PCIE_L1_PM_SUB_CNTL, &data1); in vi_program_aspm()
1182 pci_read_config_dword(adev->pdev, LINK_CAP, &data); in vi_program_aspm()
1256 vi_enable_aspm(adev); in vi_program_aspm()
1269 if ((adev->asic_type == CHIP_POLARIS12 && in vi_program_aspm()
1270 !(ASICID_IS_P23(adev->pdev->device, adev->pdev->revision))) || in vi_program_aspm()
1271 ASIC_IS_P22(adev->asic_type, adev->external_rev_id)) { in vi_program_aspm()
1279 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev, in vi_enable_doorbell_aperture() argument
1285 if (adev->flags & AMD_IS_APU) in vi_enable_doorbell_aperture()
1301 static uint32_t vi_get_rev_id(struct amdgpu_device *adev) in vi_get_rev_id() argument
1303 if (adev->flags & AMD_IS_APU) in vi_get_rev_id()
1311 static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) in vi_flush_hdp() argument
1321 static void vi_invalidate_hdp(struct amdgpu_device *adev, in vi_invalidate_hdp() argument
1332 static bool vi_need_full_reset(struct amdgpu_device *adev) in vi_need_full_reset() argument
1334 switch (adev->asic_type) { in vi_need_full_reset()
1353 static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in vi_get_pcie_usage() argument
1363 if (adev->flags & AMD_IS_APU) in vi_get_pcie_usage()
1399 static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev) in vi_get_pcie_replay_count() argument
1411 static bool vi_need_reset_on_init(struct amdgpu_device *adev) in vi_need_reset_on_init() argument
1415 if (adev->flags & AMD_IS_APU) in vi_need_reset_on_init()
1428 static void vi_pre_asic_init(struct amdgpu_device *adev) in vi_pre_asic_init() argument
1460 struct amdgpu_device *adev = ip_block->adev; in vi_common_early_init() local
1462 if (adev->flags & AMD_IS_APU) { in vi_common_early_init()
1463 adev->smc_rreg = &cz_smc_rreg; in vi_common_early_init()
1464 adev->smc_wreg = &cz_smc_wreg; in vi_common_early_init()
1466 adev->smc_rreg = &vi_smc_rreg; in vi_common_early_init()
1467 adev->smc_wreg = &vi_smc_wreg; in vi_common_early_init()
1469 adev->pcie_rreg = &vi_pcie_rreg; in vi_common_early_init()
1470 adev->pcie_wreg = &vi_pcie_wreg; in vi_common_early_init()
1471 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; in vi_common_early_init()
1472 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg; in vi_common_early_init()
1473 adev->didt_rreg = &vi_didt_rreg; in vi_common_early_init()
1474 adev->didt_wreg = &vi_didt_wreg; in vi_common_early_init()
1475 adev->gc_cac_rreg = &vi_gc_cac_rreg; in vi_common_early_init()
1476 adev->gc_cac_wreg = &vi_gc_cac_wreg; in vi_common_early_init()
1478 adev->asic_funcs = &vi_asic_funcs; in vi_common_early_init()
1480 adev->rev_id = vi_get_rev_id(adev); in vi_common_early_init()
1481 adev->external_rev_id = 0xFF; in vi_common_early_init()
1482 switch (adev->asic_type) { in vi_common_early_init()
1484 adev->cg_flags = 0; in vi_common_early_init()
1485 adev->pg_flags = 0; in vi_common_early_init()
1486 adev->external_rev_id = 0x1; in vi_common_early_init()
1489 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1506 adev->pg_flags = 0; in vi_common_early_init()
1507 adev->external_rev_id = adev->rev_id + 0x3c; in vi_common_early_init()
1510 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1523 adev->pg_flags = 0; in vi_common_early_init()
1524 adev->external_rev_id = adev->rev_id + 0x14; in vi_common_early_init()
1527 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1546 adev->pg_flags = 0; in vi_common_early_init()
1547 adev->external_rev_id = adev->rev_id + 0x5A; in vi_common_early_init()
1550 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1569 adev->pg_flags = 0; in vi_common_early_init()
1570 adev->external_rev_id = adev->rev_id + 0x50; in vi_common_early_init()
1573 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1592 adev->pg_flags = 0; in vi_common_early_init()
1593 adev->external_rev_id = adev->rev_id + 0x64; in vi_common_early_init()
1596 adev->cg_flags = 0; in vi_common_early_init()
1616 adev->pg_flags = 0; in vi_common_early_init()
1617 adev->external_rev_id = adev->rev_id + 0x6E; in vi_common_early_init()
1620 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | in vi_common_early_init()
1636 adev->pg_flags = 0; in vi_common_early_init()
1637 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) { in vi_common_early_init()
1638 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG | in vi_common_early_init()
1644 adev->external_rev_id = adev->rev_id + 0x1; in vi_common_early_init()
1647 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | in vi_common_early_init()
1661 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in vi_common_early_init()
1667 adev->external_rev_id = adev->rev_id + 0x61; in vi_common_early_init()
1674 if (amdgpu_sriov_vf(adev)) { in vi_common_early_init()
1675 amdgpu_virt_init_setting(adev); in vi_common_early_init()
1676 xgpu_vi_mailbox_set_irq_funcs(adev); in vi_common_early_init()
1684 struct amdgpu_device *adev = ip_block->adev; in vi_common_late_init() local
1686 if (amdgpu_sriov_vf(adev)) in vi_common_late_init()
1687 xgpu_vi_mailbox_get_irq(adev); in vi_common_late_init()
1694 struct amdgpu_device *adev = ip_block->adev; in vi_common_sw_init() local
1696 if (amdgpu_sriov_vf(adev)) in vi_common_sw_init()
1697 xgpu_vi_mailbox_add_irq_id(adev); in vi_common_sw_init()
1704 struct amdgpu_device *adev = ip_block->adev; in vi_common_hw_init() local
1707 vi_init_golden_registers(adev); in vi_common_hw_init()
1709 vi_program_aspm(adev); in vi_common_hw_init()
1711 vi_enable_doorbell_aperture(adev, true); in vi_common_hw_init()
1718 struct amdgpu_device *adev = ip_block->adev; in vi_common_hw_fini() local
1721 vi_enable_doorbell_aperture(adev, false); in vi_common_hw_fini()
1723 if (amdgpu_sriov_vf(adev)) in vi_common_hw_fini()
1724 xgpu_vi_mailbox_put_irq(adev); in vi_common_hw_fini()
1744 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, in vi_update_bif_medium_grain_light_sleep() argument
1751 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) in vi_update_bif_medium_grain_light_sleep()
1764 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, in vi_update_hdp_medium_grain_clock_gating() argument
1771 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) in vi_update_hdp_medium_grain_clock_gating()
1780 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev, in vi_update_hdp_light_sleep() argument
1787 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) in vi_update_hdp_light_sleep()
1796 static void vi_update_drm_light_sleep(struct amdgpu_device *adev, in vi_update_drm_light_sleep() argument
1803 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) in vi_update_drm_light_sleep()
1813 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, in vi_update_rom_medium_grain_clock_gating() argument
1820 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) in vi_update_rom_medium_grain_clock_gating()
1836 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_set_clockgating_state_by_smu() local
1838 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) { in vi_common_set_clockgating_state_by_smu()
1839 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) { in vi_common_set_clockgating_state_by_smu()
1843 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) { in vi_common_set_clockgating_state_by_smu()
1853 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1856 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) { in vi_common_set_clockgating_state_by_smu()
1857 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) { in vi_common_set_clockgating_state_by_smu()
1861 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) { in vi_common_set_clockgating_state_by_smu()
1871 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1874 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) { in vi_common_set_clockgating_state_by_smu()
1875 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { in vi_common_set_clockgating_state_by_smu()
1879 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) { in vi_common_set_clockgating_state_by_smu()
1889 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1893 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) { in vi_common_set_clockgating_state_by_smu()
1903 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1905 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) { in vi_common_set_clockgating_state_by_smu()
1915 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1918 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) { in vi_common_set_clockgating_state_by_smu()
1929 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1932 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) { in vi_common_set_clockgating_state_by_smu()
1943 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1951 struct amdgpu_device *adev = ip_block->adev; in vi_common_set_clockgating_state() local
1953 if (amdgpu_sriov_vf(adev)) in vi_common_set_clockgating_state()
1956 switch (adev->asic_type) { in vi_common_set_clockgating_state()
1958 vi_update_bif_medium_grain_light_sleep(adev, in vi_common_set_clockgating_state()
1960 vi_update_hdp_medium_grain_clock_gating(adev, in vi_common_set_clockgating_state()
1962 vi_update_hdp_light_sleep(adev, in vi_common_set_clockgating_state()
1964 vi_update_rom_medium_grain_clock_gating(adev, in vi_common_set_clockgating_state()
1969 vi_update_bif_medium_grain_light_sleep(adev, in vi_common_set_clockgating_state()
1971 vi_update_hdp_medium_grain_clock_gating(adev, in vi_common_set_clockgating_state()
1973 vi_update_hdp_light_sleep(adev, in vi_common_set_clockgating_state()
1975 vi_update_drm_light_sleep(adev, in vi_common_set_clockgating_state()
1983 vi_common_set_clockgating_state_by_smu(adev, state); in vi_common_set_clockgating_state()
1999 struct amdgpu_device *adev = ip_block->adev; in vi_common_get_clockgating_state() local
2002 if (amdgpu_sriov_vf(adev)) in vi_common_get_clockgating_state()
2050 void vi_set_virt_ops(struct amdgpu_device *adev) in vi_set_virt_ops() argument
2052 adev->virt.ops = &xgpu_vi_virt_ops; in vi_set_virt_ops()
2055 int vi_set_ip_blocks(struct amdgpu_device *adev) in vi_set_ip_blocks() argument
2057 amdgpu_device_set_sriov_virtual_display(adev); in vi_set_ip_blocks()
2059 switch (adev->asic_type) { in vi_set_ip_blocks()
2062 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2063 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block); in vi_set_ip_blocks()
2064 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block); in vi_set_ip_blocks()
2065 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2066 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block); in vi_set_ip_blocks()
2067 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2068 if (adev->enable_virtual_display) in vi_set_ip_blocks()
2069 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2072 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2073 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block); in vi_set_ip_blocks()
2074 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); in vi_set_ip_blocks()
2075 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2076 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
2077 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2078 if (adev->enable_virtual_display) in vi_set_ip_blocks()
2079 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2081 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2082 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2085 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block); in vi_set_ip_blocks()
2086 if (!amdgpu_sriov_vf(adev)) { in vi_set_ip_blocks()
2087 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); in vi_set_ip_blocks()
2088 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); in vi_set_ip_blocks()
2092 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2093 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); in vi_set_ip_blocks()
2094 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); in vi_set_ip_blocks()
2095 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2096 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
2097 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2098 if (adev->enable_virtual_display) in vi_set_ip_blocks()
2099 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2101 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2102 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2105 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block); in vi_set_ip_blocks()
2106 if (!amdgpu_sriov_vf(adev)) { in vi_set_ip_blocks()
2107 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block); in vi_set_ip_blocks()
2108 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); in vi_set_ip_blocks()
2115 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2116 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block); in vi_set_ip_blocks()
2117 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); in vi_set_ip_blocks()
2118 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2119 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block); in vi_set_ip_blocks()
2120 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2121 if (adev->enable_virtual_display) in vi_set_ip_blocks()
2122 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2124 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2125 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2128 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block); in vi_set_ip_blocks()
2129 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block); in vi_set_ip_blocks()
2130 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); in vi_set_ip_blocks()
2133 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2134 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); in vi_set_ip_blocks()
2135 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); in vi_set_ip_blocks()
2136 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2137 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
2138 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2139 if (adev->enable_virtual_display) in vi_set_ip_blocks()
2140 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2142 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2143 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2146 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); in vi_set_ip_blocks()
2147 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); in vi_set_ip_blocks()
2148 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block); in vi_set_ip_blocks()
2150 amdgpu_device_ip_block_add(adev, &acp_ip_block); in vi_set_ip_blocks()
2154 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2155 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); in vi_set_ip_blocks()
2156 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); in vi_set_ip_blocks()
2157 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block); in vi_set_ip_blocks()
2158 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
2159 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2160 if (adev->enable_virtual_display) in vi_set_ip_blocks()
2161 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2163 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2164 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2167 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); in vi_set_ip_blocks()
2168 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block); in vi_set_ip_blocks()
2169 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); in vi_set_ip_blocks()
2171 amdgpu_device_ip_block_add(adev, &acp_ip_block); in vi_set_ip_blocks()
2182 void legacy_doorbell_index_init(struct amdgpu_device *adev) in legacy_doorbell_index_init() argument
2184 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ; in legacy_doorbell_index_init()
2185 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0; in legacy_doorbell_index_init()
2186 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1; in legacy_doorbell_index_init()
2187 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2; in legacy_doorbell_index_init()
2188 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3; in legacy_doorbell_index_init()
2189 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4; in legacy_doorbell_index_init()
2190 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5; in legacy_doorbell_index_init()
2191 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6; in legacy_doorbell_index_init()
2192 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7; in legacy_doorbell_index_init()
2193 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0; in legacy_doorbell_index_init()
2194 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0; in legacy_doorbell_index_init()
2195 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1; in legacy_doorbell_index_init()
2196 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH; in legacy_doorbell_index_init()
2197 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT; in legacy_doorbell_index_init()