Lines Matching refs:pdd
316 static void kfd_init_apertures_vi(struct kfd_process_device *pdd, uint8_t id) in kfd_init_apertures_vi() argument
322 pdd->lds_base = MAKE_LDS_APP_BASE_VI(); in kfd_init_apertures_vi()
323 pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base); in kfd_init_apertures_vi()
329 pdd->gpuvm_base = max(SVM_USER_BASE, AMDGPU_VA_RESERVED_BOTTOM); in kfd_init_apertures_vi()
330 pdd->gpuvm_limit = in kfd_init_apertures_vi()
331 pdd->dev->kfd->shared_resources.gpuvm_size - 1; in kfd_init_apertures_vi()
336 pdd->qpd.cwsr_base = SVM_CWSR_BASE; in kfd_init_apertures_vi()
337 pdd->qpd.ib_base = SVM_IB_BASE; in kfd_init_apertures_vi()
339 pdd->scratch_base = MAKE_SCRATCH_APP_BASE_VI(); in kfd_init_apertures_vi()
340 pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base); in kfd_init_apertures_vi()
343 static void kfd_init_apertures_v9(struct kfd_process_device *pdd, uint8_t id) in kfd_init_apertures_v9() argument
345 pdd->lds_base = MAKE_LDS_APP_BASE_V9(); in kfd_init_apertures_v9()
346 pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base); in kfd_init_apertures_v9()
348 pdd->gpuvm_base = AMDGPU_VA_RESERVED_BOTTOM; in kfd_init_apertures_v9()
349 pdd->gpuvm_limit = in kfd_init_apertures_v9()
350 pdd->dev->kfd->shared_resources.gpuvm_size - 1; in kfd_init_apertures_v9()
352 pdd->scratch_base = MAKE_SCRATCH_APP_BASE_V9(); in kfd_init_apertures_v9()
353 pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base); in kfd_init_apertures_v9()
359 pdd->qpd.cwsr_base = AMDGPU_VA_RESERVED_TRAP_START(pdd->dev->adev); in kfd_init_apertures_v9()
366 struct kfd_process_device *pdd; in kfd_init_apertures() local
380 pdd = kfd_create_process_device_data(dev, process); in kfd_init_apertures()
381 if (!pdd) { in kfd_init_apertures()
392 pdd->lds_base = pdd->lds_limit = 0; in kfd_init_apertures()
393 pdd->gpuvm_base = pdd->gpuvm_limit = 0; in kfd_init_apertures()
394 pdd->scratch_base = pdd->scratch_limit = 0; in kfd_init_apertures()
406 kfd_init_apertures_vi(pdd, id); in kfd_init_apertures()
410 kfd_init_apertures_v9(pdd, id); in kfd_init_apertures()
420 dev_dbg(kfd_device, "gpu id %u\n", pdd->dev->id); in kfd_init_apertures()
421 dev_dbg(kfd_device, "lds_base %llX\n", pdd->lds_base); in kfd_init_apertures()
422 dev_dbg(kfd_device, "lds_limit %llX\n", pdd->lds_limit); in kfd_init_apertures()
423 dev_dbg(kfd_device, "gpuvm_base %llX\n", pdd->gpuvm_base); in kfd_init_apertures()
424 dev_dbg(kfd_device, "gpuvm_limit %llX\n", pdd->gpuvm_limit); in kfd_init_apertures()
425 dev_dbg(kfd_device, "scratch_base %llX\n", pdd->scratch_base); in kfd_init_apertures()
426 dev_dbg(kfd_device, "scratch_limit %llX\n", pdd->scratch_limit); in kfd_init_apertures()