Lines Matching refs:acrtc
276 struct amdgpu_crtc *acrtc = NULL; in dm_vblank_get_counter() local
281 acrtc = adev->mode_info.crtcs[crtc]; in dm_vblank_get_counter()
283 if (!acrtc->dm_irq_params.stream) { in dm_vblank_get_counter()
289 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); in dm_vblank_get_counter()
296 struct amdgpu_crtc *acrtc = NULL; in dm_crtc_get_scanoutpos() local
302 acrtc = adev->mode_info.crtcs[crtc]; in dm_crtc_get_scanoutpos()
304 if (!acrtc->dm_irq_params.stream) { in dm_crtc_get_scanoutpos()
317 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, in dm_crtc_get_scanoutpos()
548 struct amdgpu_crtc *acrtc; in dm_vupdate_high_irq() local
555 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); in dm_vupdate_high_irq()
557 if (acrtc) { in dm_vupdate_high_irq()
558 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); in dm_vupdate_high_irq()
559 drm_dev = acrtc->base.dev; in dm_vupdate_high_irq()
560 vblank = drm_crtc_vblank_crtc(&acrtc->base); in dm_vupdate_high_irq()
565 trace_amdgpu_refresh_rate_track(acrtc->base.index, in dm_vupdate_high_irq()
572 "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, in dm_vupdate_high_irq()
582 amdgpu_dm_crtc_handle_vblank(acrtc); in dm_vupdate_high_irq()
585 if (acrtc->dm_irq_params.stream && in dm_vupdate_high_irq()
590 acrtc->dm_irq_params.stream, in dm_vupdate_high_irq()
591 &acrtc->dm_irq_params.vrr_params); in dm_vupdate_high_irq()
595 acrtc->dm_irq_params.stream, in dm_vupdate_high_irq()
596 &acrtc->dm_irq_params.vrr_params.adjust); in dm_vupdate_high_irq()
615 struct amdgpu_crtc *acrtc; in dm_crtc_high_irq() local
619 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); in dm_crtc_high_irq()
620 if (!acrtc) in dm_crtc_high_irq()
623 if (acrtc->wb_conn) { in dm_crtc_high_irq()
624 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); in dm_crtc_high_irq()
626 if (acrtc->wb_pending) { in dm_crtc_high_irq()
627 job = list_first_entry_or_null(&acrtc->wb_conn->job_queue, in dm_crtc_high_irq()
630 acrtc->wb_pending = false; in dm_crtc_high_irq()
631 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); in dm_crtc_high_irq()
635 struct dc_stream_state *stream = acrtc->dm_irq_params.stream; in dm_crtc_high_irq()
643 drm_writeback_signal_completion(acrtc->wb_conn, 0); in dm_crtc_high_irq()
645 acrtc->dm_irq_params.stream, 0); in dm_crtc_high_irq()
648 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); in dm_crtc_high_irq()
651 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); in dm_crtc_high_irq()
654 "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, in dm_crtc_high_irq()
655 vrr_active, acrtc->dm_irq_params.active_planes); in dm_crtc_high_irq()
664 amdgpu_dm_crtc_handle_vblank(acrtc); in dm_crtc_high_irq()
670 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); in dm_crtc_high_irq()
678 if (acrtc->dm_irq_params.stream && in dm_crtc_high_irq()
679 acrtc->dm_irq_params.vrr_params.supported && in dm_crtc_high_irq()
680 acrtc->dm_irq_params.freesync_config.state == in dm_crtc_high_irq()
683 acrtc->dm_irq_params.stream, in dm_crtc_high_irq()
684 &acrtc->dm_irq_params.vrr_params); in dm_crtc_high_irq()
686 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, in dm_crtc_high_irq()
687 &acrtc->dm_irq_params.vrr_params.adjust); in dm_crtc_high_irq()
701 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && in dm_crtc_high_irq()
702 acrtc->dm_irq_params.active_planes == 0) { in dm_crtc_high_irq()
703 if (acrtc->event) { in dm_crtc_high_irq()
704 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); in dm_crtc_high_irq()
705 acrtc->event = NULL; in dm_crtc_high_irq()
706 drm_crtc_vblank_put(&acrtc->base); in dm_crtc_high_irq()
708 acrtc->pflip_status = AMDGPU_FLIP_NONE; in dm_crtc_high_irq()
726 struct amdgpu_crtc *acrtc; in dm_dcn_vertical_interrupt0_high_irq() local
728 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); in dm_dcn_vertical_interrupt0_high_irq()
730 if (!acrtc) in dm_dcn_vertical_interrupt0_high_irq()
733 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); in dm_dcn_vertical_interrupt0_high_irq()
2980 struct amdgpu_crtc *acrtc; in dm_gpureset_toggle_interrupts() local
2985 acrtc = get_crtc_by_otg_inst( in dm_gpureset_toggle_interrupts()
2988 if (acrtc && state->stream_status[i].plane_count != 0) { in dm_gpureset_toggle_interrupts()
2989 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; in dm_gpureset_toggle_interrupts()
2996 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state))) in dm_gpureset_toggle_interrupts()
2997 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true); in dm_gpureset_toggle_interrupts()
2999 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false); in dm_gpureset_toggle_interrupts()
3004 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; in dm_gpureset_toggle_interrupts()
8726 struct amdgpu_crtc *acrtc, in manage_dm_interrupts() argument
8779 drm_crtc_vblank_on_config(&acrtc->base, in manage_dm_interrupts()
8782 drm_crtc_vblank_off(&acrtc->base); in manage_dm_interrupts()
8787 struct amdgpu_crtc *acrtc) in dm_update_pflip_irq_state() argument
8790 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); in dm_update_pflip_irq_state()
8938 struct amdgpu_crtc *acrtc, in remove_stream() argument
8943 acrtc->otg_inst = -1; in remove_stream()
8944 acrtc->enabled = false; in remove_stream()
8947 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) in prepare_flip_isr() argument
8950 assert_spin_locked(&acrtc->base.dev->event_lock); in prepare_flip_isr()
8951 WARN_ON(acrtc->event); in prepare_flip_isr()
8953 acrtc->event = acrtc->base.state->event; in prepare_flip_isr()
8956 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; in prepare_flip_isr()
8959 acrtc->base.state->event = NULL; in prepare_flip_isr()
8961 drm_dbg_state(acrtc->base.dev, in prepare_flip_isr()
8963 acrtc->crtc_id); in prepare_flip_isr()
8976 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); in update_freesync_state_on_stream() local
8994 vrr_params = acrtc->dm_irq_params.vrr_params; in update_freesync_state_on_stream()
9046 acrtc->dm_irq_params.vrr_params = vrr_params; in update_freesync_state_on_stream()
9069 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); in update_stream_irq_parameters() local
9083 vrr_params = acrtc->dm_irq_params.vrr_params; in update_stream_irq_parameters()
9114 acrtc->dm_irq_params.freesync_config = config; in update_stream_irq_parameters()
9115 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; in update_stream_irq_parameters()
9116 acrtc->dm_irq_params.vrr_params = vrr_params; in update_stream_irq_parameters()
9808 struct amdgpu_crtc *acrtc; in amdgpu_dm_commit_streams() local
9819 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); in amdgpu_dm_commit_streams()
9820 if (acrtc) in amdgpu_dm_commit_streams()
9821 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); in amdgpu_dm_commit_streams()
9823 if (!acrtc || !acrtc->wb_enabled) in amdgpu_dm_commit_streams()
9829 acrtc->wb_enabled = false; in amdgpu_dm_commit_streams()
9834 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); in amdgpu_dm_commit_streams() local
9841 manage_dm_interrupts(adev, acrtc, NULL); in amdgpu_dm_commit_streams()
9850 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); in amdgpu_dm_commit_streams() local
9857 acrtc->crtc_id, in amdgpu_dm_commit_streams()
9890 acrtc->crtc_id, acrtc); in amdgpu_dm_commit_streams()
9910 acrtc->base.base.id); in amdgpu_dm_commit_streams()
9915 remove_stream(adev, acrtc, dm_old_crtc_state->stream); in amdgpu_dm_commit_streams()
9919 acrtc->enabled = true; in amdgpu_dm_commit_streams()
9920 acrtc->hw_mode = new_crtc_state->mode; in amdgpu_dm_commit_streams()
9927 acrtc->crtc_id, acrtc); in amdgpu_dm_commit_streams()
9930 remove_stream(adev, acrtc, dm_old_crtc_state->stream); in amdgpu_dm_commit_streams()
9956 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); in amdgpu_dm_commit_streams() local
9970 dm_new_crtc_state->stream, acrtc); in amdgpu_dm_commit_streams()
9972 acrtc->otg_inst = status->primary_otg_inst; in amdgpu_dm_commit_streams()
9997 struct amdgpu_crtc *acrtc; in dm_set_writeback() local
10009 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); in dm_set_writeback()
10010 if (!acrtc) { in dm_set_writeback()
10042 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; in dm_set_writeback()
10043 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; in dm_set_writeback()
10044 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; in dm_set_writeback()
10045 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; in dm_set_writeback()
10084 acrtc->wb_pending = true; in dm_set_writeback()
10085 acrtc->wb_conn = wb_conn; in dm_set_writeback()
10127 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); in amdgpu_dm_atomic_commit_tail() local
10159 if (acrtc) { in amdgpu_dm_atomic_commit_tail()
10160 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); in amdgpu_dm_atomic_commit_tail()
10161 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); in amdgpu_dm_atomic_commit_tail()
10183 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); in amdgpu_dm_atomic_commit_tail() local
10192 if (acrtc) { in amdgpu_dm_atomic_commit_tail()
10193 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); in amdgpu_dm_atomic_commit_tail()
10194 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); in amdgpu_dm_atomic_commit_tail()
10252 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); in amdgpu_dm_atomic_commit_tail() local
10261 if (acrtc) { in amdgpu_dm_atomic_commit_tail()
10262 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); in amdgpu_dm_atomic_commit_tail()
10263 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); in amdgpu_dm_atomic_commit_tail()
10267 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) in amdgpu_dm_atomic_commit_tail()
10358 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); in amdgpu_dm_atomic_commit_tail() local
10374 cur_crc_src = acrtc->dm_irq_params.crc_src; in amdgpu_dm_atomic_commit_tail()
10382 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; in amdgpu_dm_atomic_commit_tail()
10383 manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); in amdgpu_dm_atomic_commit_tail()
10402 if (acrtc->dm_irq_params.window_param[cnt].enable) { in amdgpu_dm_atomic_commit_tail()
10403 acrtc->dm_irq_params.window_param[cnt].update_win = true; in amdgpu_dm_atomic_commit_tail()
10409 acrtc->dm_irq_params.window_param[cnt].skip_frame_cnt = 2; in amdgpu_dm_atomic_commit_tail()
10438 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); in amdgpu_dm_atomic_commit_tail() local
10446 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); in amdgpu_dm_atomic_commit_tail()
10451 if (acrtc->wb_enabled) in amdgpu_dm_atomic_commit_tail()
10457 acrtc->wb_enabled = true; in amdgpu_dm_atomic_commit_tail()
10779 struct amdgpu_crtc *acrtc = NULL; in dm_update_crtc_state() local
10789 acrtc = to_amdgpu_crtc(crtc); in dm_update_crtc_state()
10827 __func__, acrtc->base.base.id); in dm_update_crtc_state()
10875 acrtc->crtc_id, in dm_update_crtc_state()
12134 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); in amdgpu_dm_atomic_check() local
12137 if (!acrtc || drm_atomic_crtc_needs_modeset( in amdgpu_dm_atomic_check()
12138 drm_atomic_get_new_crtc_state(state, &acrtc->base))) in amdgpu_dm_atomic_check()