Lines Matching refs:SR
33 SR(DMCU_CTRL), \
34 SR(DMCU_STATUS), \
35 SR(DMCU_RAM_ACCESS_CTRL), \
36 SR(DMCU_IRAM_WR_CTRL), \
37 SR(DMCU_IRAM_WR_DATA), \
38 SR(MASTER_COMM_DATA_REG1), \
39 SR(MASTER_COMM_DATA_REG2), \
40 SR(MASTER_COMM_DATA_REG3), \
41 SR(MASTER_COMM_CMD_REG), \
42 SR(MASTER_COMM_CNTL_REG), \
43 SR(SLAVE_COMM_DATA_REG1), \
44 SR(SLAVE_COMM_DATA_REG2), \
45 SR(SLAVE_COMM_DATA_REG3), \
46 SR(SLAVE_COMM_CMD_REG), \
47 SR(DMCU_IRAM_RD_CTRL), \
48 SR(DMCU_IRAM_RD_DATA), \
49 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
50 SR(SMU_INTERRUPT_CONTROL), \
51 SR(DC_DMCU_SCRATCH)
55 SR(DMCU_CTRL), \
56 SR(DMCU_STATUS), \
57 SR(DMCU_RAM_ACCESS_CTRL), \
58 SR(DMCU_IRAM_WR_CTRL), \
59 SR(DMCU_IRAM_WR_DATA), \
60 SR(MASTER_COMM_DATA_REG1), \
61 SR(MASTER_COMM_DATA_REG2), \
62 SR(MASTER_COMM_DATA_REG3), \
63 SR(MASTER_COMM_CMD_REG), \
64 SR(MASTER_COMM_CNTL_REG), \
65 SR(DMCU_IRAM_RD_CTRL), \
66 SR(DMCU_IRAM_RD_DATA), \
67 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
68 SR(DC_DMCU_SCRATCH)
72 SR(DMCU_CTRL), \
73 SR(DMCU_STATUS), \
74 SR(DMCU_RAM_ACCESS_CTRL), \
75 SR(DMCU_IRAM_WR_CTRL), \
76 SR(DMCU_IRAM_WR_DATA), \
77 SR(MASTER_COMM_DATA_REG1), \
78 SR(MASTER_COMM_DATA_REG2), \
79 SR(MASTER_COMM_DATA_REG3), \
80 SR(MASTER_COMM_CMD_REG), \
81 SR(MASTER_COMM_CNTL_REG), \
82 SR(DMCU_IRAM_RD_CTRL), \
83 SR(DMCU_IRAM_RD_DATA), \
84 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
85 SR(SMU_INTERRUPT_CONTROL), \
86 SR(DC_DMCU_SCRATCH)
90 SR(DCI_MEM_PWR_STATUS)
94 SR(DMU_MEM_PWR_CNTL)
98 SR(DMCUB_SCRATCH15)