Lines Matching refs:performance_levels
2433 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()
2434 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()
2452 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2453 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2459 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2468 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
2527 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
3197 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= in ni_set_uvd_clock_before_set_eng_clock()
3198 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_before_set_eng_clock()
3215 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < in ni_set_uvd_clock_after_set_eng_clock()
3216 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_after_set_eng_clock()
3504 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()
3505 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()
3509 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
3510 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3511 if (ps->performance_levels[i].sclk > max_limits->sclk) in si_apply_state_adjust_rules()
3512 ps->performance_levels[i].sclk = max_limits->sclk; in si_apply_state_adjust_rules()
3513 if (ps->performance_levels[i].vddc > max_limits->vddc) in si_apply_state_adjust_rules()
3514 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
3515 if (ps->performance_levels[i].vddci > max_limits->vddci) in si_apply_state_adjust_rules()
3516 ps->performance_levels[i].vddci = max_limits->vddci; in si_apply_state_adjust_rules()
3530 if (ps->performance_levels[i].sclk > max_sclk_vddc) in si_apply_state_adjust_rules()
3531 ps->performance_levels[i].sclk = max_sclk_vddc; in si_apply_state_adjust_rules()
3534 if (ps->performance_levels[i].mclk > max_mclk_vddci) in si_apply_state_adjust_rules()
3535 ps->performance_levels[i].mclk = max_mclk_vddci; in si_apply_state_adjust_rules()
3538 if (ps->performance_levels[i].mclk > max_mclk_vddc) in si_apply_state_adjust_rules()
3539 ps->performance_levels[i].mclk = max_mclk_vddc; in si_apply_state_adjust_rules()
3542 if (ps->performance_levels[i].mclk > max_mclk) in si_apply_state_adjust_rules()
3543 ps->performance_levels[i].mclk = max_mclk; in si_apply_state_adjust_rules()
3546 if (ps->performance_levels[i].sclk > max_sclk) in si_apply_state_adjust_rules()
3547 ps->performance_levels[i].sclk = max_sclk; in si_apply_state_adjust_rules()
3554 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()
3555 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; in si_apply_state_adjust_rules()
3557 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3558 vddci = ps->performance_levels[0].vddci; in si_apply_state_adjust_rules()
3562 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; in si_apply_state_adjust_rules()
3563 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; in si_apply_state_adjust_rules()
3565 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3566 vddc = ps->performance_levels[0].vddc; in si_apply_state_adjust_rules()
3577 ps->performance_levels[0].sclk = sclk; in si_apply_state_adjust_rules()
3578 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3579 ps->performance_levels[0].vddc = vddc; in si_apply_state_adjust_rules()
3580 ps->performance_levels[0].vddci = vddci; in si_apply_state_adjust_rules()
3583 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3585 if (sclk < ps->performance_levels[i].sclk) in si_apply_state_adjust_rules()
3586 sclk = ps->performance_levels[i].sclk; in si_apply_state_adjust_rules()
3589 ps->performance_levels[i].sclk = sclk; in si_apply_state_adjust_rules()
3590 ps->performance_levels[i].vddc = vddc; in si_apply_state_adjust_rules()
3594 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in si_apply_state_adjust_rules()
3595 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in si_apply_state_adjust_rules()
3596 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in si_apply_state_adjust_rules()
3597 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in si_apply_state_adjust_rules()
3602 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3604 if (mclk < ps->performance_levels[i].mclk) in si_apply_state_adjust_rules()
3605 mclk = ps->performance_levels[i].mclk; in si_apply_state_adjust_rules()
3608 ps->performance_levels[i].mclk = mclk; in si_apply_state_adjust_rules()
3609 ps->performance_levels[i].vddci = vddci; in si_apply_state_adjust_rules()
3613 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in si_apply_state_adjust_rules()
3614 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in si_apply_state_adjust_rules()
3615 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) in si_apply_state_adjust_rules()
3616 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; in si_apply_state_adjust_rules()
3622 &ps->performance_levels[i]); in si_apply_state_adjust_rules()
3625 if (ps->performance_levels[i].vddc < min_vce_voltage) in si_apply_state_adjust_rules()
3626 ps->performance_levels[i].vddc = min_vce_voltage; in si_apply_state_adjust_rules()
3628 ps->performance_levels[i].sclk, in si_apply_state_adjust_rules()
3629 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3631 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3632 max_limits->vddci, &ps->performance_levels[i].vddci); in si_apply_state_adjust_rules()
3634 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3635 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3638 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3644 &ps->performance_levels[i].vddc, in si_apply_state_adjust_rules()
3645 &ps->performance_levels[i].vddci); in si_apply_state_adjust_rules()
3650 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
4808 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); in si_do_program_memory_timing_parameters()
4876 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4892 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state()
4900 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4918 initial_state->performance_levels[0].vddci, in si_populate_smc_initial_state()
4924 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4925 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state()
4926 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4939 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4941 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
5615 state->performance_levels[i + 1].sclk, in si_populate_smc_t()
5616 state->performance_levels[i].sclk, in si_populate_smc_t()
5658 if (state->performance_levels[0].mclk != ulv->pl.mclk) in si_is_state_ulv_compatible()
5707 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; in si_convert_power_state_to_smc()
5731 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i], in si_convert_power_state_to_smc()
5741 (state->performance_levels[i].sclk < threshold) ? in si_convert_power_state_to_smc()
6139 &state->performance_levels[i], in si_convert_mc_reg_table_to_smc()
6158 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0], in si_populate_mc_reg_table()
6218 pcie_speed = state->performance_levels[i].pcie_gen; in si_get_maximum_link_speed()
7208 struct rv7xx_pl *pl = &ps->performance_levels[index]; in si_parse_pplib_clock_info()
7561 pl = &ps->performance_levels[current_index]; in si_dpm_debugfs_print_current_performance_level()
7928 return requested_state->performance_levels[0].sclk; in si_dpm_get_sclk()
7930 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; in si_dpm_get_sclk()
7940 return requested_state->performance_levels[0].mclk; in si_dpm_get_mclk()
7942 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; in si_dpm_get_mclk()
7958 pl = &ps->performance_levels[i]; in si_dpm_print_power_state()
8016 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]), in si_check_state_equal()
8017 &(si_rps->performance_levels[i]))) { in si_check_state_equal()
8049 sclk = ps->performance_levels[pl_index].sclk; in si_dpm_read_sensor()
8057 mclk = ps->performance_levels[pl_index].mclk; in si_dpm_read_sensor()