Lines Matching refs:regmap
201 struct regmap *regmap; member
338 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_bridge_disable()
339 regmap_update_bits(priv->regmap, 0x52, RESETDB, 0x00); in ch7033_bridge_disable()
346 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_bridge_enable()
347 regmap_update_bits(priv->regmap, 0x52, RESETDB, RESETDB); in ch7033_bridge_enable()
363 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_bridge_mode_set()
366 regmap_write(priv->regmap, 0x52, 0x00); in ch7033_bridge_mode_set()
368 regmap_write(priv->regmap, 0x52, RESETIB); in ch7033_bridge_mode_set()
373 regmap_write(priv->regmap, 0x03, 0x00); in ch7033_bridge_mode_set()
376 regmap_update_bits(priv->regmap, 0x07, DRI_PD | IO_PD, 0); in ch7033_bridge_mode_set()
377 regmap_update_bits(priv->regmap, 0x08, DRI_PDDRI | PDDAC | PANEN, 0); in ch7033_bridge_mode_set()
378 regmap_update_bits(priv->regmap, 0x09, DPD | GCKOFF | in ch7033_bridge_mode_set()
380 regmap_update_bits(priv->regmap, 0x0a, HD_DVIB, 0); in ch7033_bridge_mode_set()
383 regmap_write(priv->regmap, 0x0b, (mode->htotal >> 8) << 3 | in ch7033_bridge_mode_set()
385 regmap_write(priv->regmap, 0x0c, mode->hdisplay); in ch7033_bridge_mode_set()
386 regmap_write(priv->regmap, 0x0d, mode->htotal); in ch7033_bridge_mode_set()
387 regmap_write(priv->regmap, 0x0e, (hsynclen >> 8) << 3 | in ch7033_bridge_mode_set()
389 regmap_write(priv->regmap, 0x0f, hbporch); in ch7033_bridge_mode_set()
390 regmap_write(priv->regmap, 0x10, hsynclen); in ch7033_bridge_mode_set()
393 regmap_write(priv->regmap, 0x11, (mode->vtotal >> 8) << 3 | in ch7033_bridge_mode_set()
395 regmap_write(priv->regmap, 0x12, mode->vdisplay); in ch7033_bridge_mode_set()
396 regmap_write(priv->regmap, 0x13, mode->vtotal); in ch7033_bridge_mode_set()
397 regmap_write(priv->regmap, 0x14, ((vsynclen >> 8) << 3) | in ch7033_bridge_mode_set()
399 regmap_write(priv->regmap, 0x15, vbporch); in ch7033_bridge_mode_set()
400 regmap_write(priv->regmap, 0x16, vsynclen); in ch7033_bridge_mode_set()
403 regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR); in ch7033_bridge_mode_set()
406 regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16); in ch7033_bridge_mode_set()
407 regmap_update_bits(priv->regmap, 0x19, HPO_I | VPO_I | GCLKFREQ, in ch7033_bridge_mode_set()
411 regmap_write(priv->regmap, 0x1a, mode->clock >> 8); in ch7033_bridge_mode_set()
412 regmap_write(priv->regmap, 0x1b, mode->clock); in ch7033_bridge_mode_set()
415 regmap_write(priv->regmap, 0x1f, (mode->htotal >> 8) << 3 | in ch7033_bridge_mode_set()
417 regmap_write(priv->regmap, 0x20, mode->hdisplay); in ch7033_bridge_mode_set()
418 regmap_write(priv->regmap, 0x21, mode->htotal); in ch7033_bridge_mode_set()
421 regmap_write(priv->regmap, 0x25, (mode->vtotal >> 8) << 3 | in ch7033_bridge_mode_set()
423 regmap_write(priv->regmap, 0x26, mode->vdisplay); in ch7033_bridge_mode_set()
424 regmap_write(priv->regmap, 0x27, mode->vtotal); in ch7033_bridge_mode_set()
427 regmap_update_bits(priv->regmap, 0x2b, VFMT, 9); in ch7033_bridge_mode_set()
430 regmap_update_bits(priv->regmap, 0x2e, HPO_O | VPO_O, in ch7033_bridge_mode_set()
435 regmap_update_bits(priv->regmap, 0x54, HWO_HDMI_HI | HOO_HDMI_HI, in ch7033_bridge_mode_set()
438 regmap_write(priv->regmap, 0x55, hbporch); in ch7033_bridge_mode_set()
439 regmap_write(priv->regmap, 0x56, hsynclen); in ch7033_bridge_mode_set()
442 regmap_update_bits(priv->regmap, 0x57, VWO_HDMI_HI | VOO_HDMI_HI, in ch7033_bridge_mode_set()
445 regmap_write(priv->regmap, 0x58, vbporch); in ch7033_bridge_mode_set()
446 regmap_write(priv->regmap, 0x59, vsynclen); in ch7033_bridge_mode_set()
449 regmap_update_bits(priv->regmap, 0x7e, HDMI_LVDS_SEL, HDMI_LVDS_SEL); in ch7033_bridge_mode_set()
454 regmap_write(priv->regmap, 0x03, 0x01); in ch7033_bridge_mode_set()
457 regmap_update_bits(priv->regmap, 0x07, CKINV, CKINV); in ch7033_bridge_mode_set()
458 regmap_update_bits(priv->regmap, 0x08, DISPON, DISPON); in ch7033_bridge_mode_set()
461 regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_DIVSEL, DRI_PLL_DIVSEL); in ch7033_bridge_mode_set()
463 regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 | in ch7033_bridge_mode_set()
469 regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 | in ch7033_bridge_mode_set()
476 regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 | in ch7033_bridge_mode_set()
485 regmap_write(priv->regmap, 0x64, 0x29); /* LSB Blue */ in ch7033_bridge_mode_set()
486 regmap_write(priv->regmap, 0x65, 0x29); /* LSB Green */ in ch7033_bridge_mode_set()
487 regmap_write(priv->regmap, 0x66, 0x29); /* LSB Red */ in ch7033_bridge_mode_set()
488 regmap_write(priv->regmap, 0x67, 0x00); /* MSB Blue */ in ch7033_bridge_mode_set()
489 regmap_write(priv->regmap, 0x68, 0x00); /* MSB Green */ in ch7033_bridge_mode_set()
490 regmap_write(priv->regmap, 0x69, 0x00); /* MSB Red */ in ch7033_bridge_mode_set()
492 regmap_update_bits(priv->regmap, 0x6b, DRI_PD_SER, 0x00); in ch7033_bridge_mode_set()
493 regmap_update_bits(priv->regmap, 0x6c, DRI_PLL_PD, 0x00); in ch7033_bridge_mode_set()
498 regmap_write(priv->regmap, 0x03, 0x03); in ch7033_bridge_mode_set()
501 regmap_update_bits(priv->regmap, 0x28, VGACLK_BP | HM_LV_SEL, in ch7033_bridge_mode_set()
503 regmap_update_bits(priv->regmap, 0x2a, HDMICLK_BP | HDMI_BP, in ch7033_bridge_mode_set()
509 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_bridge_mode_set()
512 regmap_write(priv->regmap, 0x10, mode->clock >> 16); in ch7033_bridge_mode_set()
513 regmap_write(priv->regmap, 0x11, mode->clock >> 8); in ch7033_bridge_mode_set()
514 regmap_write(priv->regmap, 0x12, mode->clock); in ch7033_bridge_mode_set()
551 priv->regmap = devm_regmap_init_i2c(client, &ch7033_regmap_config); in ch7033_probe()
552 if (IS_ERR(priv->regmap)) { in ch7033_probe()
554 return PTR_ERR(priv->regmap); in ch7033_probe()
557 ret = regmap_read(priv->regmap, 0x00, &val); in ch7033_probe()
567 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_probe()
568 ret = regmap_read(priv->regmap, 0x51, &val); in ch7033_probe()