Lines Matching refs:dpcd
287 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in __read_delay()
303 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in __read_delay()
329 rd_interval = dpcd[offset]; in __read_delay()
342 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_clock_recovery_delay()
345 return __read_delay(aux, dpcd, dp_phy, uhbr, true); in drm_dp_read_clock_recovery_delay()
349 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_channel_eq_delay()
352 return __read_delay(aux, dpcd, dp_phy, uhbr, false); in drm_dp_read_channel_eq_delay()
377 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_clock_recovery_delay()
379 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_clock_recovery_delay()
383 if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in drm_dp_link_train_clock_recovery_delay()
401 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_channel_eq_delay()
404 dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_channel_eq_delay()
1065 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_is_type()
1068 return drm_dp_is_branch(dpcd) && in drm_dp_downstream_is_type()
1069 dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_downstream_is_type()
1082 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_is_tmds()
1086 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_is_tmds()
1087 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_is_tmds()
1169 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_downstream_port_count()
1171 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK; in drm_dp_downstream_port_count()
1173 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4) in drm_dp_downstream_port_count()
1180 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_extended_dpcd_caps()
1192 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_read_extended_dpcd_caps()
1201 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { in drm_dp_read_extended_dpcd_caps()
1204 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); in drm_dp_read_extended_dpcd_caps()
1208 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) in drm_dp_read_extended_dpcd_caps()
1211 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); in drm_dp_read_extended_dpcd_caps()
1213 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); in drm_dp_read_extended_dpcd_caps()
1232 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_dpcd_caps()
1236 ret = drm_dp_dpcd_read_data(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_read_dpcd_caps()
1239 if (dpcd[DP_DPCD_REV] == 0) in drm_dp_read_dpcd_caps()
1242 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd); in drm_dp_read_dpcd_caps()
1246 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); in drm_dp_read_dpcd_caps()
1266 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_downstream_info()
1275 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) in drm_dp_read_downstream_info()
1282 len = drm_dp_downstream_port_count(dpcd); in drm_dp_read_downstream_info()
1286 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) in drm_dp_read_downstream_info()
1307 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_dotclock()
1310 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_dotclock()
1313 if (dpcd[DP_DPCD_REV] < 0x11) in drm_dp_downstream_max_dotclock()
1318 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_dotclock()
1336 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_tmds_clock()
1340 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_tmds_clock()
1343 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_max_tmds_clock()
1344 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_max_tmds_clock()
1378 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_tmds_clock()
1382 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_tmds_clock()
1401 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_min_tmds_clock()
1405 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_min_tmds_clock()
1408 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_min_tmds_clock()
1409 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_min_tmds_clock()
1444 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_bpc()
1448 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_bpc()
1451 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_max_bpc()
1452 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_max_bpc()
1470 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_bpc()
1500 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_420_passthrough()
1503 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_420_passthrough()
1506 if (dpcd[DP_DPCD_REV] < 0x13) in drm_dp_downstream_420_passthrough()
1513 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_420_passthrough()
1531 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_444_to_420_conversion()
1534 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_444_to_420_conversion()
1537 if (dpcd[DP_DPCD_REV] < 0x13) in drm_dp_downstream_444_to_420_conversion()
1542 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_444_to_420_conversion()
1562 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_rgb_to_ycbcr_conversion()
1566 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_rgb_to_ycbcr_conversion()
1569 if (dpcd[DP_DPCD_REV] < 0x13) in drm_dp_downstream_rgb_to_ycbcr_conversion()
1574 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_rgb_to_ycbcr_conversion()
1596 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_mode()
1602 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_mode()
1605 if (dpcd[DP_DPCD_REV] < 0x11) in drm_dp_downstream_mode()
1662 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_debug()
1667 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & in drm_dp_downstream_debug()
1675 bool branch_device = drm_dp_is_branch(dpcd); in drm_dp_downstream_debug()
1723 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap); in drm_dp_downstream_debug()
1727 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, drm_edid); in drm_dp_downstream_debug()
1731 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, drm_edid); in drm_dp_downstream_debug()
1735 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, drm_edid); in drm_dp_downstream_debug()
1749 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_subconnector_type()
1753 if (!drm_dp_is_branch(dpcd)) in drm_dp_subconnector_type()
1756 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) { in drm_dp_subconnector_type()
1757 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] & in drm_dp_subconnector_type()
1806 const u8 *dpcd, in drm_dp_set_subconnector_property() argument
1812 subconnector = drm_dp_subconnector_type(dpcd, port_cap); in drm_dp_set_subconnector_property()
1832 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_sink_count_cap()
1837 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 && in drm_dp_read_sink_count_cap()
1838 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && in drm_dp_read_sink_count_cap()
2836 const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address, in drm_dp_read_lttpr_regs()
2844 int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size; in drm_dp_read_lttpr_regs()
2870 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_lttpr_common_caps()
2873 return drm_dp_read_lttpr_regs(aux, dpcd, in drm_dp_read_lttpr_common_caps()
2891 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_lttpr_phy_caps()
2895 return drm_dp_read_lttpr_regs(aux, dpcd, in drm_dp_read_lttpr_phy_caps()
3331 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_as_sdp_supported()
3335 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13) in drm_dp_as_sdp_supported()
3356 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_vsc_sdp_supported()
3360 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13) in drm_dp_vsc_sdp_supported()
3454 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_get_pcon_max_frl_bw()