Lines Matching refs:bits_per_pixel
124 ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> in drm_dsc_pps_payload_pack()
133 (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK); in drm_dsc_pps_payload_pack()
325 if (vdsc_cfg->bits_per_pixel == 6 << 4) { in drm_dsc_set_rc_buf_thresh()
1250 if (WARN_ON_ONCE(!vdsc_cfg->bits_per_pixel || in drm_dsc_setup_rc_params()
1272 vdsc_cfg->bits_per_pixel, in drm_dsc_setup_rc_params()
1330 vdsc_cfg->bits_per_pixel, in drm_dsc_compute_rc_parameters()
1339 vdsc_cfg->bits_per_pixel, in drm_dsc_compute_rc_parameters()
1374 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; in drm_dsc_compute_rc_parameters()
1430 vdsc_cfg->bits_per_pixel, 16) + in drm_dsc_compute_rc_parameters()
1433 hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); in drm_dsc_compute_rc_parameters()
1434 vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; in drm_dsc_compute_rc_parameters()
1449 WARN_ON_ONCE(vdsc_cfg->bits_per_pixel & 0xf); in drm_dsc_get_bpp_int()
1450 return vdsc_cfg->bits_per_pixel >> 4; in drm_dsc_get_bpp_int()
1493 cfg->bits_per_component, FXP_Q4_ARGS(cfg->bits_per_pixel), cfg->line_buf_depth); in drm_dsc_dump_config_main_params()