Lines Matching refs:gpu_write
501 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
503 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
560 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
563 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
568 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
576 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
580 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
603 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
695 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); in etnaviv_gpu_start_fe()
696 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
701 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
776 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); in etnaviv_gpu_hw_init()
786 gpu_write(gpu, VIVS_HI_AXI_CONFIG, in etnaviv_gpu_hw_init()
797 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); in etnaviv_gpu_hw_init()
803 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); in etnaviv_gpu_hw_init()
809 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); in etnaviv_gpu_hw_init()