Lines Matching refs:cdv

238 	pci_read_config_byte(pdev, 0xF4, &regs->cdv.saveLBB);  in cdv_save_display_registers()
240 	regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);  in cdv_save_display_registers()
241 	regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);  in cdv_save_display_registers()
243 	regs->cdv.saveDSPARB = REG_READ(DSPARB);  in cdv_save_display_registers()
244 	regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);  in cdv_save_display_registers()
245 	regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);  in cdv_save_display_registers()
246 	regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);  in cdv_save_display_registers()
247 	regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);  in cdv_save_display_registers()
248 	regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);  in cdv_save_display_registers()
249 	regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);  in cdv_save_display_registers()
251 	regs->cdv.saveADPA = REG_READ(ADPA);  in cdv_save_display_registers()
253 	regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);  in cdv_save_display_registers()
254 	regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);  in cdv_save_display_registers()
257 	regs->cdv.saveLVDS = REG_READ(LVDS);  in cdv_save_display_registers()
259 	regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);  in cdv_save_display_registers()
261 	regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);  in cdv_save_display_registers()
262 	regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);  in cdv_save_display_registers()
263 	regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);  in cdv_save_display_registers()
265 	regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);  in cdv_save_display_registers()
267 	regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);  in cdv_save_display_registers()
268 	regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);  in cdv_save_display_registers()
295 	pci_write_config_byte(pdev, 0xF4, regs->cdv.saveLBB);  in cdv_restore_display_registers()
297 	REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);  in cdv_restore_display_registers()
298 	REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);  in cdv_restore_display_registers()
318 	REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);  in cdv_restore_display_registers()
319 	REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);  in cdv_restore_display_registers()
320 	REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);  in cdv_restore_display_registers()
321 	REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);  in cdv_restore_display_registers()
322 	REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);  in cdv_restore_display_registers()
323 	REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);  in cdv_restore_display_registers()
325 	REG_WRITE(DSPARB, regs->cdv.saveDSPARB);  in cdv_restore_display_registers()
326 	REG_WRITE(ADPA, regs->cdv.saveADPA);  in cdv_restore_display_registers()
329 	REG_WRITE(LVDS, regs->cdv.saveLVDS);  in cdv_restore_display_registers()
330 	REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);  in cdv_restore_display_registers()
331 	REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);  in cdv_restore_display_registers()
333 	REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);  in cdv_restore_display_registers()
334 	REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);  in cdv_restore_display_registers()
335 	REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);  in cdv_restore_display_registers()
336 	REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);  in cdv_restore_display_registers()
338 	REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);  in cdv_restore_display_registers()
340 	REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);  in cdv_restore_display_registers()
341 	REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);  in cdv_restore_display_registers()