Lines Matching refs:REG_WRITE
140 REG_WRITE(SB_ADDR, reg); in cdv_sb_read()
141 REG_WRITE(SB_PCKT, in cdv_sb_read()
175 REG_WRITE(SB_ADDR, reg); in cdv_sb_write()
176 REG_WRITE(SB_DATA, val); in cdv_sb_write()
177 REG_WRITE(SB_PCKT, in cdv_sb_write()
202 REG_WRITE(DPIO_CFG, 0); in cdv_sb_reset()
204 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); in cdv_sb_reset()
227 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()
475 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
483 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); in cdv_disable_sr()
505 REG_WRITE(DSPFW1, fw); in cdv_update_wm()
512 REG_WRITE(DSPFW2, fw); in cdv_update_wm()
514 REG_WRITE(DSPFW3, 0x36000000); in cdv_update_wm()
521 REG_WRITE(DSPFW5, 0x00040330); in cdv_update_wm()
527 REG_WRITE(DSPFW5, fw); in cdv_update_wm()
530 REG_WRITE(DSPFW6, 0x10); in cdv_update_wm()
535 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); in cdv_update_wm()
542 REG_WRITE(DSPFW1, 0x3f880808); in cdv_update_wm()
543 REG_WRITE(DSPFW2, 0x0b020202); in cdv_update_wm()
544 REG_WRITE(DSPFW3, 0x24000000); in cdv_update_wm()
545 REG_WRITE(DSPFW4, 0x08030202); in cdv_update_wm()
546 REG_WRITE(DSPFW5, 0x01010101); in cdv_update_wm()
547 REG_WRITE(DSPFW6, 0x1d0); in cdv_update_wm()
670 REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0); in cdv_intel_crtc_mode_set()
671 REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0); in cdv_intel_crtc_mode_set()
672 REG_WRITE(PIPE_DP_LINK_M(pipe), 0); in cdv_intel_crtc_mode_set()
673 REG_WRITE(PIPE_DP_LINK_N(pipe), 0); in cdv_intel_crtc_mode_set()
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
754 REG_WRITE(LVDS, lvds); in cdv_intel_crtc_mode_set()
762 REG_WRITE(PFIT_CONTROL, 0); in cdv_intel_crtc_mode_set()
767 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
780 …REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_U… in cdv_intel_crtc_mode_set()
783 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in cdv_intel_crtc_mode_set()
785 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in cdv_intel_crtc_mode_set()
787 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in cdv_intel_crtc_mode_set()
789 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | in cdv_intel_crtc_mode_set()
791 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | in cdv_intel_crtc_mode_set()
793 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | in cdv_intel_crtc_mode_set()
798 REG_WRITE(map->size, in cdv_intel_crtc_mode_set()
800 REG_WRITE(map->pos, 0); in cdv_intel_crtc_mode_set()
801 REG_WRITE(map->src, in cdv_intel_crtc_mode_set()
803 REG_WRITE(map->conf, pipeconf); in cdv_intel_crtc_mode_set()
808 REG_WRITE(map->cntr, dspcntr); in cdv_intel_crtc_mode_set()