Lines Matching refs:cdclk
160 u8 (*calc_voltage_level)(int cdclk);
166 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
173 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); in intel_cdclk_set_cdclk()
180 return display->funcs.cdclk->modeset_calc_cdclk(state); in intel_cdclk_modeset_calc_cdclk()
184 int cdclk) in intel_cdclk_calc_voltage_level() argument
186 return display->funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
192 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
198 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
204 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
210 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
216 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
222 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
237 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
251 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
254 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
257 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
262 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
276 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
282 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
286 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
300 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
306 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
310 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
423 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
431 cdclk_config->cdclk = 190476; in g33_get_cdclk()
444 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
447 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
450 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
453 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
460 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
463 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
502 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
510 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
530 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
533 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
539 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
551 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
553 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
555 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
557 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
559 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
583 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) in vlv_calc_voltage_level() argument
588 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ in vlv_calc_voltage_level()
590 else if (cdclk >= 266667) in vlv_calc_voltage_level()
600 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
612 cdclk_config->cdclk = vlv_get_cck_clock(display->drm, "cdclk", in vlv_get_cdclk()
639 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
672 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk() local
676 switch (cdclk) { in vlv_set_cdclk()
684 MISSING_CASE(cdclk); in vlv_set_cdclk()
712 if (cdclk == 400000) { in vlv_set_cdclk()
716 cdclk) - 1; in vlv_set_cdclk()
739 if (cdclk == 400000) in vlv_set_cdclk()
761 int cdclk = cdclk_config->cdclk; in chv_set_cdclk() local
765 switch (cdclk) { in chv_set_cdclk()
772 MISSING_CASE(cdclk); in chv_set_cdclk()
817 static u8 bdw_calc_voltage_level(int cdclk) in bdw_calc_voltage_level() argument
819 switch (cdclk) { in bdw_calc_voltage_level()
839 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
841 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
843 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
845 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
847 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
849 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
856 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
859 static u32 bdw_cdclk_freq_sel(int cdclk) in bdw_cdclk_freq_sel() argument
861 switch (cdclk) { in bdw_cdclk_freq_sel()
863 MISSING_CASE(cdclk); in bdw_cdclk_freq_sel()
880 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk() local
911 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); in bdw_set_cdclk()
924 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); in bdw_set_cdclk()
952 static u8 skl_calc_voltage_level(int cdclk) in skl_calc_voltage_level() argument
954 if (cdclk > 540000) in skl_calc_voltage_level()
956 else if (cdclk > 450000) in skl_calc_voltage_level()
958 else if (cdclk > 337500) in skl_calc_voltage_level()
1012 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
1022 cdclk_config->cdclk = 432000; in skl_get_cdclk()
1025 cdclk_config->cdclk = 308571; in skl_get_cdclk()
1028 cdclk_config->cdclk = 540000; in skl_get_cdclk()
1031 cdclk_config->cdclk = 617143; in skl_get_cdclk()
1040 cdclk_config->cdclk = 450000; in skl_get_cdclk()
1043 cdclk_config->cdclk = 337500; in skl_get_cdclk()
1046 cdclk_config->cdclk = 540000; in skl_get_cdclk()
1049 cdclk_config->cdclk = 675000; in skl_get_cdclk()
1063 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
1067 static int skl_cdclk_decimal(int cdclk) in skl_cdclk_decimal() argument
1069 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); in skl_cdclk_decimal()
1074 bool changed = display->cdclk.skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
1076 display->cdclk.skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
1117 display->cdclk.hw.vco = vco; in skl_dpll0_enable()
1131 display->cdclk.hw.vco = 0; in skl_dpll0_disable()
1135 int cdclk, int vco) in skl_cdclk_freq_sel() argument
1137 switch (cdclk) { in skl_cdclk_freq_sel()
1140 cdclk != display->cdclk.hw.bypass); in skl_cdclk_freq_sel()
1161 int cdclk = cdclk_config->cdclk; in skl_set_cdclk() local
1187 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); in skl_set_cdclk()
1189 if (display->cdclk.hw.vco != 0 && in skl_set_cdclk()
1190 display->cdclk.hw.vco != vco) in skl_set_cdclk()
1195 if (display->cdclk.hw.vco != vco) { in skl_set_cdclk()
1198 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); in skl_set_cdclk()
1207 if (display->cdclk.hw.vco != vco) in skl_set_cdclk()
1214 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); in skl_set_cdclk()
1242 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1245 if (display->cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1246 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in skl_sanitize_cdclk()
1257 skl_cdclk_decimal(display->cdclk.hw.cdclk); in skl_sanitize_cdclk()
1266 display->cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1268 display->cdclk.hw.vco = ~0; in skl_sanitize_cdclk()
1277 if (display->cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1278 display->cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1283 if (display->cdclk.skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1285 display->cdclk.hw.vco); in skl_cdclk_init_hw()
1289 cdclk_config = display->cdclk.hw; in skl_cdclk_init_hw()
1291 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; in skl_cdclk_init_hw()
1294 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); in skl_cdclk_init_hw()
1295 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_init_hw()
1302 struct intel_cdclk_config cdclk_config = display->cdclk.hw; in skl_cdclk_uninit_hw()
1304 cdclk_config.cdclk = cdclk_config.bypass; in skl_cdclk_uninit_hw()
1306 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_uninit_hw()
1312 u32 cdclk; member
1319 { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1320 { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1321 { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1322 { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1323 { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
1328 { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
1329 { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
1330 { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
1335 { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
1336 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1337 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1338 { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
1339 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1340 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1342 { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
1343 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1344 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1345 { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
1346 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1347 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1349 { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
1350 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1351 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1352 { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
1353 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1354 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1359 { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
1360 { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
1361 { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
1362 { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
1363 { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
1364 { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
1366 { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
1367 { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
1368 { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
1369 { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
1370 { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
1371 { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
1373 { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
1374 { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
1375 { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
1376 { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
1377 { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
1378 { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
1383 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1384 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1385 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1387 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1388 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1389 { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
1391 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1392 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1393 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1398 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1399 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1400 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1401 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1402 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1404 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1405 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1406 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1407 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1408 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1410 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1411 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1412 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1413 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1414 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1419 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1420 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1421 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1422 { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
1423 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1424 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1426 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1427 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1428 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1429 { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
1430 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1431 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1433 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1434 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1435 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1436 { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
1437 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1438 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1443 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
1444 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
1445 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
1446 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
1447 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
1448 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
1449 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
1450 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
1451 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
1452 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
1453 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1454 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1455 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1460 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1461 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1462 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
1463 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
1464 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
1465 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
1470 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1471 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1472 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1473 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1474 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1475 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1476 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1477 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1478 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1479 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
1480 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
1481 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
1482 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
1483 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
1484 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1485 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
1486 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
1487 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1488 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1489 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1490 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1498 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1503 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1504 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1505 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1506 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1507 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1508 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1509 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1510 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1511 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1512 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff },
1513 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff },
1514 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff },
1515 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff },
1516 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
1517 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
1518 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
1519 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
1520 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1521 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
1522 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
1523 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
1524 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1525 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
1526 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
1527 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
1528 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
1529 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1530 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
1531 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
1542 static int cdclk_divider(int cdclk, int vco, u16 waveform) in cdclk_divider() argument
1546 cdclk * cdclk_squash_len); in cdclk_divider()
1551 const struct intel_cdclk_vals *table = display->cdclk.table; in bxt_calc_cdclk()
1555 if (table[i].refclk == display->cdclk.hw.ref && in bxt_calc_cdclk()
1556 table[i].cdclk >= min_cdclk) in bxt_calc_cdclk()
1557 return table[i].cdclk; in bxt_calc_cdclk()
1561 min_cdclk, display->cdclk.hw.ref); in bxt_calc_cdclk()
1565 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) in bxt_calc_cdclk_pll_vco() argument
1567 const struct intel_cdclk_vals *table = display->cdclk.table; in bxt_calc_cdclk_pll_vco()
1570 if (cdclk == display->cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1574 if (table[i].refclk == display->cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1575 table[i].cdclk == cdclk) in bxt_calc_cdclk_pll_vco()
1576 return display->cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1579 cdclk, display->cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1583 static u8 bxt_calc_voltage_level(int cdclk) in bxt_calc_voltage_level() argument
1585 return DIV_ROUND_UP(cdclk, 25000); in bxt_calc_voltage_level()
1588 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, in calc_voltage_level() argument
1594 if (cdclk <= voltage_level_max_cdclk[voltage_level]) in calc_voltage_level()
1598 MISSING_CASE(cdclk); in calc_voltage_level()
1602 static u8 icl_calc_voltage_level(int cdclk) in icl_calc_voltage_level() argument
1610 return calc_voltage_level(cdclk, in icl_calc_voltage_level()
1615 static u8 ehl_calc_voltage_level(int cdclk) in ehl_calc_voltage_level() argument
1628 return calc_voltage_level(cdclk, in ehl_calc_voltage_level()
1633 static u8 tgl_calc_voltage_level(int cdclk) in tgl_calc_voltage_level() argument
1642 return calc_voltage_level(cdclk, in tgl_calc_voltage_level()
1647 static u8 rplu_calc_voltage_level(int cdclk) in rplu_calc_voltage_level() argument
1656 return calc_voltage_level(cdclk, in rplu_calc_voltage_level()
1661 static u8 xe3lpd_calc_voltage_level(int cdclk) in xe3lpd_calc_voltage_level() argument
1744 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1778 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * in bxt_get_cdclk()
1781 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1792 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); in bxt_get_cdclk()
1804 display->cdclk.hw.vco = 0; in bxt_de_pll_disable()
1809 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in bxt_de_pll_enable()
1821 display->cdclk.hw.vco = vco; in bxt_de_pll_enable()
1833 display->cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1838 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in icl_cdclk_pll_enable()
1851 display->cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1856 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1875 display->cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1899 int cdclk, int vco, u16 waveform) in bxt_cdclk_cd2x_div_sel() argument
1902 switch (cdclk_divider(cdclk, vco, waveform)) { in bxt_cdclk_cd2x_div_sel()
1905 cdclk != display->cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1920 int cdclk) in cdclk_squash_waveform() argument
1922 const struct intel_cdclk_vals *table = display->cdclk.table; in cdclk_squash_waveform()
1925 if (cdclk == display->cdclk.hw.bypass) in cdclk_squash_waveform()
1929 if (table[i].refclk == display->cdclk.hw.ref && in cdclk_squash_waveform()
1930 table[i].cdclk == cdclk) in cdclk_squash_waveform()
1934 cdclk, display->cdclk.hw.ref); in cdclk_squash_waveform()
1941 if (display->cdclk.hw.vco != 0 && in icl_cdclk_pll_update()
1942 display->cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1945 if (display->cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1951 if (display->cdclk.hw.vco != 0 && in bxt_cdclk_pll_update()
1952 display->cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1955 if (display->cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1998 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); in intel_mdclk_cdclk_ratio()
2028 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
2029 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
2037 old_div = cdclk_divider(old_cdclk_config->cdclk, in cdclk_compute_crawl_and_squash_midpoint()
2039 new_div = cdclk_divider(new_cdclk_config->cdclk, in cdclk_compute_crawl_and_squash_midpoint()
2069 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * in cdclk_compute_crawl_and_squash_midpoint()
2075 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < in cdclk_compute_crawl_and_squash_midpoint()
2076 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); in cdclk_compute_crawl_and_squash_midpoint()
2077 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > in cdclk_compute_crawl_and_squash_midpoint()
2078 display->cdclk.max_cdclk_freq); in cdclk_compute_crawl_and_squash_midpoint()
2079 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != in cdclk_compute_crawl_and_squash_midpoint()
2090 display->cdclk.hw.vco > 0; in pll_enable_wa_needed()
2097 int cdclk = cdclk_config->cdclk; in bxt_cdclk_ctl() local
2102 waveform = cdclk_squash_waveform(display, cdclk); in bxt_cdclk_ctl()
2104 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | in bxt_cdclk_ctl()
2112 cdclk >= 500000) in bxt_cdclk_ctl()
2118 val |= skl_cdclk_decimal(cdclk); in bxt_cdclk_ctl()
2127 int cdclk = cdclk_config->cdclk; in _bxt_set_cdclk() local
2130 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
2131 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { in _bxt_set_cdclk()
2132 if (display->cdclk.hw.vco != vco) in _bxt_set_cdclk()
2145 u16 waveform = cdclk_squash_waveform(display, cdclk); in _bxt_set_cdclk()
2161 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk() local
2189 ret, cdclk); in bxt_set_cdclk()
2193 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) in bxt_set_cdclk()
2196 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, in bxt_set_cdclk()
2204 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) in bxt_set_cdclk()
2229 ret, cdclk); in bxt_set_cdclk()
2240 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
2246 int cdclk, vco; in bxt_sanitize_cdclk() local
2249 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
2251 if (display->cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
2252 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in bxt_sanitize_cdclk()
2256 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2257 if (cdclk != display->cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2261 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_sanitize_cdclk()
2262 if (vco != display->cdclk.hw.vco) in bxt_sanitize_cdclk()
2271 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); in bxt_sanitize_cdclk()
2289 display->cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
2292 display->cdclk.hw.vco = ~0; in bxt_sanitize_cdclk()
2301 if (display->cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2302 display->cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2305 cdclk_config = display->cdclk.hw; in bxt_cdclk_init_hw()
2312 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); in bxt_cdclk_init_hw()
2313 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2315 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2322 struct intel_cdclk_config cdclk_config = display->cdclk.hw; in bxt_cdclk_uninit_hw()
2324 cdclk_config.cdclk = cdclk_config.bypass; in bxt_cdclk_uninit_hw()
2327 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
2379 old_waveform = cdclk_squash_waveform(display, a->cdclk); in intel_cdclk_can_crawl_and_squash()
2380 new_waveform = cdclk_squash_waveform(display, b->cdclk); in intel_cdclk_can_crawl_and_squash()
2399 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); in intel_cdclk_can_crawl()
2400 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); in intel_cdclk_can_crawl()
2421 return a->cdclk != b->cdclk && in intel_cdclk_can_squash()
2439 return a->cdclk != b->cdclk || in intel_cdclk_clock_changed()
2472 return a->cdclk != b->cdclk && in intel_cdclk_can_cd2x_update()
2498 context, cdclk_config->cdclk, cdclk_config->vco, in intel_cdclk_dump_config()
2506 u16 cdclk, in intel_pcode_notify() argument
2516 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); in intel_pcode_notify()
2541 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) in intel_set_cdclk()
2544 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2588 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), in intel_set_cdclk()
2590 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); in intel_set_cdclk()
2602 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; in intel_cdclk_pcode_pre_notify() local
2614 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_pre_notify()
2625 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); in intel_cdclk_pcode_pre_notify()
2636 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_pre_notify()
2647 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; in intel_cdclk_pcode_post_notify() local
2653 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2662 cdclk = new_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2673 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_post_notify()
2685 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; in intel_cdclk_is_decreasing_later()
2717 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { in intel_set_cdclk_pre_plane_update()
2766 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) in intel_set_cdclk_post_plane_update()
2895 if (min_cdclk > display->cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2898 min_cdclk, display->cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2960 int min_cdclk, cdclk; in vlv_modeset_calc_cdclk() local
2966 cdclk = vlv_calc_cdclk(display, min_cdclk); in vlv_modeset_calc_cdclk()
2968 cdclk_state->logical.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2970 vlv_calc_voltage_level(display, cdclk); in vlv_modeset_calc_cdclk()
2973 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2975 cdclk_state->actual.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2977 vlv_calc_voltage_level(display, cdclk); in vlv_modeset_calc_cdclk()
2989 int min_cdclk, cdclk; in bdw_modeset_calc_cdclk() local
2995 cdclk = bdw_calc_cdclk(min_cdclk); in bdw_modeset_calc_cdclk()
2997 cdclk_state->logical.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2999 bdw_calc_voltage_level(cdclk); in bdw_modeset_calc_cdclk()
3002 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); in bdw_modeset_calc_cdclk()
3004 cdclk_state->actual.cdclk = cdclk; in bdw_modeset_calc_cdclk()
3006 bdw_calc_voltage_level(cdclk); in bdw_modeset_calc_cdclk()
3025 vco = display->cdclk.skl_preferred_vco_freq; in skl_dpll0_vco()
3056 int min_cdclk, cdclk, vco; in skl_modeset_calc_cdclk() local
3064 cdclk = skl_calc_cdclk(min_cdclk, vco); in skl_modeset_calc_cdclk()
3067 cdclk_state->logical.cdclk = cdclk; in skl_modeset_calc_cdclk()
3069 skl_calc_voltage_level(cdclk); in skl_modeset_calc_cdclk()
3072 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); in skl_modeset_calc_cdclk()
3075 cdclk_state->actual.cdclk = cdclk; in skl_modeset_calc_cdclk()
3077 skl_calc_voltage_level(cdclk); in skl_modeset_calc_cdclk()
3090 int min_cdclk, min_voltage_level, cdclk, vco; in bxt_modeset_calc_cdclk() local
3100 cdclk = bxt_calc_cdclk(display, min_cdclk); in bxt_modeset_calc_cdclk()
3101 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_modeset_calc_cdclk()
3104 cdclk_state->logical.cdclk = cdclk; in bxt_modeset_calc_cdclk()
3107 intel_cdclk_calc_voltage_level(display, cdclk)); in bxt_modeset_calc_cdclk()
3110 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
3111 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_modeset_calc_cdclk()
3114 cdclk_state->actual.cdclk = cdclk; in bxt_modeset_calc_cdclk()
3116 intel_cdclk_calc_voltage_level(display, cdclk); in bxt_modeset_calc_cdclk()
3171 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); in intel_atomic_get_cdclk_state()
3235 intel_atomic_global_obj_init(display, &display->cdclk.obj, in intel_cdclk_init()
3359 new_cdclk_state->logical.cdclk, in intel_modeset_calc_cdclk()
3360 new_cdclk_state->actual.cdclk); in intel_modeset_calc_cdclk()
3374 to_intel_cdclk_state(display->cdclk.obj.state); in intel_cdclk_update_hw_state()
3405 int max_cdclk_freq = display->cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
3421 display->cdclk.max_cdclk_freq = 480000; in intel_update_max_cdclk()
3423 display->cdclk.max_cdclk_freq = 691200; in intel_update_max_cdclk()
3425 if (display->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3426 display->cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
3428 display->cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
3430 if (display->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3431 display->cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
3433 display->cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
3435 display->cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
3437 display->cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3442 vco = display->cdclk.skl_preferred_vco_freq; in intel_update_max_cdclk()
3459 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3468 display->cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3470 display->cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3472 display->cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3474 display->cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3476 display->cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3478 display->cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3481 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; in intel_update_max_cdclk()
3484 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); in intel_update_max_cdclk()
3487 display->cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3490 display->cdclk.max_dotclk_freq); in intel_update_max_cdclk()
3501 intel_cdclk_get_cdclk(display, &display->cdclk.hw); in intel_update_cdclk()
3511 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3614 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); in i915_cdclk_info_show()
3615 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); in i915_cdclk_info_show()
3616 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); in i915_cdclk_info_show()
3781 display->funcs.cdclk = &xe3lpd_cdclk_funcs; in intel_init_cdclk_hooks()
3782 display->cdclk.table = xe3lpd_cdclk_table; in intel_init_cdclk_hooks()
3784 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3785 display->cdclk.table = xe2lpd_cdclk_table; in intel_init_cdclk_hooks()
3787 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3788 display->cdclk.table = xe2hpd_cdclk_table; in intel_init_cdclk_hooks()
3790 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3791 display->cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3793 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3794 display->cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3798 display->cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3799 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3801 display->cdclk.table = rplu_cdclk_table; in intel_init_cdclk_hooks()
3802 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3804 display->cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3805 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3808 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3809 display->cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3811 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3812 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3814 display->funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3815 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3817 display->funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3818 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3820 display->funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3822 display->cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3824 display->cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3826 display->funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3828 display->funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3830 display->funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3832 display->funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3834 display->funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3836 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3838 display->funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3840 display->funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3842 display->funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3844 display->funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3846 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3848 display->funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3850 display->funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3852 display->funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3854 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3856 display->funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3858 display->funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3860 display->funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3862 display->funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3864 display->funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3866 display->funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3869 if (drm_WARN(display->drm, !display->funcs.cdclk, in intel_init_cdclk_hooks()
3871 display->funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3876 return cdclk_state->logical.cdclk; in intel_cdclk_logical()
3881 return cdclk_state->actual.cdclk; in intel_cdclk_actual()
3907 (new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk || in intel_cdclk_pmdemand_needs_update()
3923 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); in intel_cdclk_read_hw()
3926 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in intel_cdclk_read_hw()
3927 cdclk_state->actual = display->cdclk.hw; in intel_cdclk_read_hw()
3928 cdclk_state->logical = display->cdclk.hw; in intel_cdclk_read_hw()