Lines Matching refs:display
154 void (*get_cdclk)(struct intel_display *display,
156 void (*set_cdclk)(struct intel_display *display,
163 void intel_cdclk_get_cdclk(struct intel_display *display, in intel_cdclk_get_cdclk() argument
166 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
169 static void intel_cdclk_set_cdclk(struct intel_display *display, in intel_cdclk_set_cdclk() argument
173 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); in intel_cdclk_set_cdclk()
178 struct intel_display *display = to_intel_display(state); in intel_cdclk_modeset_calc_cdclk() local
180 return display->funcs.cdclk->modeset_calc_cdclk(state); in intel_cdclk_modeset_calc_cdclk()
183 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, in intel_cdclk_calc_voltage_level() argument
186 return display->funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
189 static void fixed_133mhz_get_cdclk(struct intel_display *display, in fixed_133mhz_get_cdclk() argument
195 static void fixed_200mhz_get_cdclk(struct intel_display *display, in fixed_200mhz_get_cdclk() argument
201 static void fixed_266mhz_get_cdclk(struct intel_display *display, in fixed_266mhz_get_cdclk() argument
207 static void fixed_333mhz_get_cdclk(struct intel_display *display, in fixed_333mhz_get_cdclk() argument
213 static void fixed_400mhz_get_cdclk(struct intel_display *display, in fixed_400mhz_get_cdclk() argument
219 static void fixed_450mhz_get_cdclk(struct intel_display *display, in fixed_450mhz_get_cdclk() argument
225 static void i85x_get_cdclk(struct intel_display *display, in i85x_get_cdclk() argument
228 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i85x_get_cdclk()
267 static void i915gm_get_cdclk(struct intel_display *display, in i915gm_get_cdclk() argument
270 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i915gm_get_cdclk()
291 static void i945gm_get_cdclk(struct intel_display *display, in i945gm_get_cdclk() argument
294 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i945gm_get_cdclk()
315 static unsigned int intel_hpll_vco(struct intel_display *display) in intel_hpll_vco() argument
359 if (display->platform.gm45) in intel_hpll_vco()
361 else if (display->platform.g45) in intel_hpll_vco()
363 else if (display->platform.i965gm) in intel_hpll_vco()
365 else if (display->platform.pineview) in intel_hpll_vco()
367 else if (display->platform.g33) in intel_hpll_vco()
372 tmp = intel_de_read(display, display->platform.pineview || in intel_hpll_vco()
373 display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO); in intel_hpll_vco()
377 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
380 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
385 static void g33_get_cdclk(struct intel_display *display, in g33_get_cdclk() argument
388 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in g33_get_cdclk()
397 cdclk_config->vco = intel_hpll_vco(display); in g33_get_cdclk()
428 drm_err(display->drm, in g33_get_cdclk()
434 static void pnv_get_cdclk(struct intel_display *display, in pnv_get_cdclk() argument
437 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in pnv_get_cdclk()
456 drm_err(display->drm, in pnv_get_cdclk()
468 static void i965gm_get_cdclk(struct intel_display *display, in i965gm_get_cdclk() argument
471 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i965gm_get_cdclk()
479 cdclk_config->vco = intel_hpll_vco(display); in i965gm_get_cdclk()
507 drm_err(display->drm, in i965gm_get_cdclk()
513 static void gm45_get_cdclk(struct intel_display *display, in gm45_get_cdclk() argument
516 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in gm45_get_cdclk()
520 cdclk_config->vco = intel_hpll_vco(display); in gm45_get_cdclk()
536 drm_err(display->drm, in gm45_get_cdclk()
544 static void hsw_get_cdclk(struct intel_display *display, in hsw_get_cdclk() argument
547 u32 lcpll = intel_de_read(display, LCPLL_CTL); in hsw_get_cdclk()
552 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) in hsw_get_cdclk()
556 else if (display->platform.haswell_ult) in hsw_get_cdclk()
562 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) in vlv_calc_cdclk() argument
564 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_calc_cdclk()
573 if (display->platform.valleyview && min_cdclk > freq_320) in vlv_calc_cdclk()
583 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) in vlv_calc_voltage_level() argument
585 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_calc_voltage_level()
587 if (display->platform.valleyview) { in vlv_calc_voltage_level()
604 static void vlv_get_cdclk(struct intel_display *display, in vlv_get_cdclk() argument
609 vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); in vlv_get_cdclk()
611 cdclk_config->vco = vlv_get_hpll_vco(display->drm); in vlv_get_cdclk()
612 cdclk_config->cdclk = vlv_get_cck_clock(display->drm, "cdclk", in vlv_get_cdclk()
616 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); in vlv_get_cdclk()
618 vlv_iosf_sb_put(display->drm, in vlv_get_cdclk()
621 if (display->platform.valleyview) in vlv_get_cdclk()
629 static void vlv_program_pfi_credits(struct intel_display *display) in vlv_program_pfi_credits() argument
631 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_program_pfi_credits()
634 if (display->platform.cherryview) in vlv_program_pfi_credits()
639 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
641 if (display->platform.cherryview) in vlv_program_pfi_credits()
653 intel_de_write(display, GCI_CONTROL, in vlv_program_pfi_credits()
656 intel_de_write(display, GCI_CONTROL, in vlv_program_pfi_credits()
663 drm_WARN_ON(display->drm, in vlv_program_pfi_credits()
664 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
667 static void vlv_set_cdclk(struct intel_display *display, in vlv_set_cdclk() argument
671 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_set_cdclk()
694 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); in vlv_set_cdclk()
696 vlv_iosf_sb_get(display->drm, in vlv_set_cdclk()
701 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); in vlv_set_cdclk()
704 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); in vlv_set_cdclk()
705 if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & in vlv_set_cdclk()
708 drm_err(display->drm, in vlv_set_cdclk()
719 val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL); in vlv_set_cdclk()
722 vlv_cck_write(display->drm, CCK_DISPLAY_CLOCK_CONTROL, val); in vlv_set_cdclk()
724 if (wait_for((vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL) & in vlv_set_cdclk()
727 drm_err(display->drm, in vlv_set_cdclk()
732 val = vlv_bunit_read(display->drm, BUNIT_REG_BISOC); in vlv_set_cdclk()
743 vlv_bunit_write(display->drm, BUNIT_REG_BISOC, val); in vlv_set_cdclk()
745 vlv_iosf_sb_put(display->drm, in vlv_set_cdclk()
750 intel_update_cdclk(display); in vlv_set_cdclk()
752 vlv_program_pfi_credits(display); in vlv_set_cdclk()
754 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); in vlv_set_cdclk()
757 static void chv_set_cdclk(struct intel_display *display, in chv_set_cdclk() argument
782 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); in chv_set_cdclk()
784 vlv_punit_get(display->drm); in chv_set_cdclk()
785 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); in chv_set_cdclk()
788 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); in chv_set_cdclk()
789 if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & in chv_set_cdclk()
792 drm_err(display->drm, in chv_set_cdclk()
796 vlv_punit_put(display->drm); in chv_set_cdclk()
798 intel_update_cdclk(display); in chv_set_cdclk()
800 vlv_program_pfi_credits(display); in chv_set_cdclk()
802 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); in chv_set_cdclk()
832 static void bdw_get_cdclk(struct intel_display *display, in bdw_get_cdclk() argument
835 u32 lcpll = intel_de_read(display, LCPLL_CTL); in bdw_get_cdclk()
840 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) in bdw_get_cdclk()
876 static void bdw_set_cdclk(struct intel_display *display, in bdw_set_cdclk() argument
883 if (drm_WARN(display->drm, in bdw_set_cdclk()
884 (intel_de_read(display, LCPLL_CTL) & in bdw_set_cdclk()
892 ret = intel_pcode_write(display->drm, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); in bdw_set_cdclk()
894 drm_err(display->drm, in bdw_set_cdclk()
899 intel_de_rmw(display, LCPLL_CTL, in bdw_set_cdclk()
906 if (wait_for_us(intel_de_read(display, LCPLL_CTL) & in bdw_set_cdclk()
908 drm_err(display->drm, "Switching to FCLK failed\n"); in bdw_set_cdclk()
910 intel_de_rmw(display, LCPLL_CTL, in bdw_set_cdclk()
913 intel_de_rmw(display, LCPLL_CTL, in bdw_set_cdclk()
916 if (wait_for_us((intel_de_read(display, LCPLL_CTL) & in bdw_set_cdclk()
918 drm_err(display->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
920 intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
923 intel_de_write(display, CDCLK_FREQ, in bdw_set_cdclk()
926 intel_update_cdclk(display); in bdw_set_cdclk()
964 static void skl_dpll0_update(struct intel_display *display, in skl_dpll0_update() argument
972 val = intel_de_read(display, LCPLL1_CTL); in skl_dpll0_update()
976 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) in skl_dpll0_update()
979 val = intel_de_read(display, DPLL_CTRL1); in skl_dpll0_update()
981 if (drm_WARN_ON(display->drm, in skl_dpll0_update()
1005 static void skl_get_cdclk(struct intel_display *display, in skl_get_cdclk() argument
1010 skl_dpll0_update(display, cdclk_config); in skl_get_cdclk()
1017 cdctl = intel_de_read(display, CDCLK_CTL); in skl_get_cdclk()
1072 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) in skl_set_preferred_cdclk_vco() argument
1074 bool changed = display->cdclk.skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
1076 display->cdclk.skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
1079 intel_update_max_cdclk(display); in skl_set_preferred_cdclk_vco()
1082 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) in skl_dpll0_link_rate() argument
1084 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_link_rate()
1101 static void skl_dpll0_enable(struct intel_display *display, int vco) in skl_dpll0_enable() argument
1103 intel_de_rmw(display, DPLL_CTRL1, in skl_dpll0_enable()
1108 skl_dpll0_link_rate(display, vco)); in skl_dpll0_enable()
1109 intel_de_posting_read(display, DPLL_CTRL1); in skl_dpll0_enable()
1111 intel_de_rmw(display, LCPLL1_CTL, in skl_dpll0_enable()
1114 if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) in skl_dpll0_enable()
1115 drm_err(display->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
1117 display->cdclk.hw.vco = vco; in skl_dpll0_enable()
1120 skl_set_preferred_cdclk_vco(display, vco); in skl_dpll0_enable()
1123 static void skl_dpll0_disable(struct intel_display *display) in skl_dpll0_disable() argument
1125 intel_de_rmw(display, LCPLL1_CTL, in skl_dpll0_disable()
1128 if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) in skl_dpll0_disable()
1129 drm_err(display->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
1131 display->cdclk.hw.vco = 0; in skl_dpll0_disable()
1134 static u32 skl_cdclk_freq_sel(struct intel_display *display, in skl_cdclk_freq_sel() argument
1139 drm_WARN_ON(display->drm, in skl_cdclk_freq_sel()
1140 cdclk != display->cdclk.hw.bypass); in skl_cdclk_freq_sel()
1141 drm_WARN_ON(display->drm, vco != 0); in skl_cdclk_freq_sel()
1157 static void skl_set_cdclk(struct intel_display *display, in skl_set_cdclk() argument
1174 drm_WARN_ON_ONCE(display->drm, in skl_set_cdclk()
1175 display->platform.skylake && vco == 8640000); in skl_set_cdclk()
1177 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1182 drm_err(display->drm, in skl_set_cdclk()
1187 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); in skl_set_cdclk()
1189 if (display->cdclk.hw.vco != 0 && in skl_set_cdclk()
1190 display->cdclk.hw.vco != vco) in skl_set_cdclk()
1191 skl_dpll0_disable(display); in skl_set_cdclk()
1193 cdclk_ctl = intel_de_read(display, CDCLK_CTL); in skl_set_cdclk()
1195 if (display->cdclk.hw.vco != vco) { in skl_set_cdclk()
1199 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1204 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1205 intel_de_posting_read(display, CDCLK_CTL); in skl_set_cdclk()
1207 if (display->cdclk.hw.vco != vco) in skl_set_cdclk()
1208 skl_dpll0_enable(display, vco); in skl_set_cdclk()
1212 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1215 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1219 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1220 intel_de_posting_read(display, CDCLK_CTL); in skl_set_cdclk()
1223 intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1226 intel_update_cdclk(display); in skl_set_cdclk()
1229 static void skl_sanitize_cdclk(struct intel_display *display) in skl_sanitize_cdclk() argument
1238 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) in skl_sanitize_cdclk()
1241 intel_update_cdclk(display); in skl_sanitize_cdclk()
1242 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1245 if (display->cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1246 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in skl_sanitize_cdclk()
1255 cdctl = intel_de_read(display, CDCLK_CTL); in skl_sanitize_cdclk()
1257 skl_cdclk_decimal(display->cdclk.hw.cdclk); in skl_sanitize_cdclk()
1263 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1266 display->cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1268 display->cdclk.hw.vco = ~0; in skl_sanitize_cdclk()
1271 static void skl_cdclk_init_hw(struct intel_display *display) in skl_cdclk_init_hw() argument
1275 skl_sanitize_cdclk(display); in skl_cdclk_init_hw()
1277 if (display->cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1278 display->cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1283 if (display->cdclk.skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1284 skl_set_preferred_cdclk_vco(display, in skl_cdclk_init_hw()
1285 display->cdclk.hw.vco); in skl_cdclk_init_hw()
1289 cdclk_config = display->cdclk.hw; in skl_cdclk_init_hw()
1291 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; in skl_cdclk_init_hw()
1297 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); in skl_cdclk_init_hw()
1300 static void skl_cdclk_uninit_hw(struct intel_display *display) in skl_cdclk_uninit_hw() argument
1302 struct intel_cdclk_config cdclk_config = display->cdclk.hw; in skl_cdclk_uninit_hw()
1308 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); in skl_cdclk_uninit_hw()
1549 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) in bxt_calc_cdclk() argument
1551 const struct intel_cdclk_vals *table = display->cdclk.table; in bxt_calc_cdclk()
1555 if (table[i].refclk == display->cdclk.hw.ref && in bxt_calc_cdclk()
1559 drm_WARN(display->drm, 1, in bxt_calc_cdclk()
1561 min_cdclk, display->cdclk.hw.ref); in bxt_calc_cdclk()
1565 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) in bxt_calc_cdclk_pll_vco() argument
1567 const struct intel_cdclk_vals *table = display->cdclk.table; in bxt_calc_cdclk_pll_vco()
1570 if (cdclk == display->cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1574 if (table[i].refclk == display->cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1576 return display->cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1578 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1579 cdclk, display->cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1671 static void icl_readout_refclk(struct intel_display *display, in icl_readout_refclk() argument
1674 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; in icl_readout_refclk()
1692 static void bxt_de_pll_readout(struct intel_display *display, in bxt_de_pll_readout() argument
1697 if (display->platform.dg2) in bxt_de_pll_readout()
1699 else if (DISPLAY_VER(display) >= 11) in bxt_de_pll_readout()
1700 icl_readout_refclk(display, cdclk_config); in bxt_de_pll_readout()
1704 val = intel_de_read(display, BXT_DE_PLL_ENABLE); in bxt_de_pll_readout()
1719 if (DISPLAY_VER(display) >= 11) in bxt_de_pll_readout()
1722 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; in bxt_de_pll_readout()
1727 static void bxt_get_cdclk(struct intel_display *display, in bxt_get_cdclk() argument
1734 bxt_de_pll_readout(display, cdclk_config); in bxt_get_cdclk()
1736 if (DISPLAY_VER(display) >= 12) in bxt_get_cdclk()
1738 else if (DISPLAY_VER(display) >= 11) in bxt_get_cdclk()
1748 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; in bxt_get_cdclk()
1768 if (HAS_CDCLK_SQUASH(display)) in bxt_get_cdclk()
1769 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); in bxt_get_cdclk()
1785 if (DISPLAY_VER(display) >= 20) in bxt_get_cdclk()
1786 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; in bxt_get_cdclk()
1792 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); in bxt_get_cdclk()
1795 static void bxt_de_pll_disable(struct intel_display *display) in bxt_de_pll_disable() argument
1797 intel_de_write(display, BXT_DE_PLL_ENABLE, 0); in bxt_de_pll_disable()
1800 if (intel_de_wait_for_clear(display, in bxt_de_pll_disable()
1802 drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); in bxt_de_pll_disable()
1804 display->cdclk.hw.vco = 0; in bxt_de_pll_disable()
1807 static void bxt_de_pll_enable(struct intel_display *display, int vco) in bxt_de_pll_enable() argument
1809 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in bxt_de_pll_enable()
1811 intel_de_rmw(display, BXT_DE_PLL_CTL, in bxt_de_pll_enable()
1814 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); in bxt_de_pll_enable()
1817 if (intel_de_wait_for_set(display, in bxt_de_pll_enable()
1819 drm_err(display->drm, "timeout waiting for DE PLL lock\n"); in bxt_de_pll_enable()
1821 display->cdclk.hw.vco = vco; in bxt_de_pll_enable()
1824 static void icl_cdclk_pll_disable(struct intel_display *display) in icl_cdclk_pll_disable() argument
1826 intel_de_rmw(display, BXT_DE_PLL_ENABLE, in icl_cdclk_pll_disable()
1830 if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) in icl_cdclk_pll_disable()
1831 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1833 display->cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1836 static void icl_cdclk_pll_enable(struct intel_display *display, int vco) in icl_cdclk_pll_enable() argument
1838 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in icl_cdclk_pll_enable()
1842 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in icl_cdclk_pll_enable()
1845 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in icl_cdclk_pll_enable()
1848 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) in icl_cdclk_pll_enable()
1849 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1851 display->cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1854 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) in adlp_cdclk_pll_crawl() argument
1856 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1861 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1865 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1868 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, in adlp_cdclk_pll_crawl()
1870 drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); in adlp_cdclk_pll_crawl()
1873 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1875 display->cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1878 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) in bxt_cdclk_cd2x_pipe() argument
1880 if (DISPLAY_VER(display) >= 12) { in bxt_cdclk_cd2x_pipe()
1885 } else if (DISPLAY_VER(display) >= 11) { in bxt_cdclk_cd2x_pipe()
1898 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, in bxt_cdclk_cd2x_div_sel() argument
1904 drm_WARN_ON(display->drm, in bxt_cdclk_cd2x_div_sel()
1905 cdclk != display->cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1906 drm_WARN_ON(display->drm, vco != 0); in bxt_cdclk_cd2x_div_sel()
1919 static u16 cdclk_squash_waveform(struct intel_display *display, in cdclk_squash_waveform() argument
1922 const struct intel_cdclk_vals *table = display->cdclk.table; in cdclk_squash_waveform()
1925 if (cdclk == display->cdclk.hw.bypass) in cdclk_squash_waveform()
1929 if (table[i].refclk == display->cdclk.hw.ref && in cdclk_squash_waveform()
1933 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1934 cdclk, display->cdclk.hw.ref); in cdclk_squash_waveform()
1939 static void icl_cdclk_pll_update(struct intel_display *display, int vco) in icl_cdclk_pll_update() argument
1941 if (display->cdclk.hw.vco != 0 && in icl_cdclk_pll_update()
1942 display->cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1943 icl_cdclk_pll_disable(display); in icl_cdclk_pll_update()
1945 if (display->cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1946 icl_cdclk_pll_enable(display, vco); in icl_cdclk_pll_update()
1949 static void bxt_cdclk_pll_update(struct intel_display *display, int vco) in bxt_cdclk_pll_update() argument
1951 if (display->cdclk.hw.vco != 0 && in bxt_cdclk_pll_update()
1952 display->cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1953 bxt_de_pll_disable(display); in bxt_cdclk_pll_update()
1955 if (display->cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1956 bxt_de_pll_enable(display, vco); in bxt_cdclk_pll_update()
1959 static void dg2_cdclk_squash_program(struct intel_display *display, in dg2_cdclk_squash_program() argument
1968 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); in dg2_cdclk_squash_program()
1981 static bool mdclk_source_is_cdclk_pll(struct intel_display *display) in mdclk_source_is_cdclk_pll() argument
1983 return DISPLAY_VER(display) >= 20; in mdclk_source_is_cdclk_pll()
1986 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) in xe2lpd_mdclk_source_sel() argument
1988 if (mdclk_source_is_cdclk_pll(display)) in xe2lpd_mdclk_source_sel()
1994 int intel_mdclk_cdclk_ratio(struct intel_display *display, in intel_mdclk_cdclk_ratio() argument
1997 if (mdclk_source_is_cdclk_pll(display)) in intel_mdclk_cdclk_ratio()
2004 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, in xe2lpd_mdclk_cdclk_ratio_program() argument
2007 intel_dbuf_mdclk_cdclk_ratio_update(display, in xe2lpd_mdclk_cdclk_ratio_program()
2008 intel_mdclk_cdclk_ratio(display, cdclk_config), in xe2lpd_mdclk_cdclk_ratio_program()
2012 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, in cdclk_compute_crawl_and_squash_midpoint() argument
2025 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) in cdclk_compute_crawl_and_squash_midpoint()
2028 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
2029 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
2046 if (drm_WARN_ON(display->drm, old_div != new_div)) in cdclk_compute_crawl_and_squash_midpoint()
2075 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < in cdclk_compute_crawl_and_squash_midpoint()
2077 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > in cdclk_compute_crawl_and_squash_midpoint()
2078 display->cdclk.max_cdclk_freq); in cdclk_compute_crawl_and_squash_midpoint()
2079 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != in cdclk_compute_crawl_and_squash_midpoint()
2085 static bool pll_enable_wa_needed(struct intel_display *display) in pll_enable_wa_needed() argument
2087 return (DISPLAY_VERx100(display) == 2000 || in pll_enable_wa_needed()
2088 DISPLAY_VERx100(display) == 1400 || in pll_enable_wa_needed()
2089 display->platform.dg2) && in pll_enable_wa_needed()
2090 display->cdclk.hw.vco > 0; in pll_enable_wa_needed()
2093 static u32 bxt_cdclk_ctl(struct intel_display *display, in bxt_cdclk_ctl() argument
2102 waveform = cdclk_squash_waveform(display, cdclk); in bxt_cdclk_ctl()
2104 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | in bxt_cdclk_ctl()
2105 bxt_cdclk_cd2x_pipe(display, pipe); in bxt_cdclk_ctl()
2111 if ((display->platform.geminilake || display->platform.broxton) && in bxt_cdclk_ctl()
2115 if (DISPLAY_VER(display) >= 20) in bxt_cdclk_ctl()
2116 val |= xe2lpd_mdclk_source_sel(display); in bxt_cdclk_ctl()
2123 static void _bxt_set_cdclk(struct intel_display *display, in _bxt_set_cdclk() argument
2130 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
2131 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { in _bxt_set_cdclk()
2132 if (display->cdclk.hw.vco != vco) in _bxt_set_cdclk()
2133 adlp_cdclk_pll_crawl(display, vco); in _bxt_set_cdclk()
2134 } else if (DISPLAY_VER(display) >= 11) { in _bxt_set_cdclk()
2136 if (pll_enable_wa_needed(display)) in _bxt_set_cdclk()
2137 dg2_cdclk_squash_program(display, 0); in _bxt_set_cdclk()
2139 icl_cdclk_pll_update(display, vco); in _bxt_set_cdclk()
2141 bxt_cdclk_pll_update(display, vco); in _bxt_set_cdclk()
2144 if (HAS_CDCLK_SQUASH(display)) { in _bxt_set_cdclk()
2145 u16 waveform = cdclk_squash_waveform(display, cdclk); in _bxt_set_cdclk()
2147 dg2_cdclk_squash_program(display, waveform); in _bxt_set_cdclk()
2150 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); in _bxt_set_cdclk()
2153 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); in _bxt_set_cdclk()
2156 static void bxt_set_cdclk(struct intel_display *display, in bxt_set_cdclk() argument
2170 if (DISPLAY_VER(display) >= 14 || display->platform.dg2) in bxt_set_cdclk()
2172 else if (DISPLAY_VER(display) >= 11) in bxt_set_cdclk()
2173 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
2182 ret = intel_pcode_write_timeout(display->drm, in bxt_set_cdclk()
2187 drm_err(display->drm, in bxt_set_cdclk()
2193 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) in bxt_set_cdclk()
2194 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); in bxt_set_cdclk()
2196 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, in bxt_set_cdclk()
2198 _bxt_set_cdclk(display, &mid_cdclk_config, pipe); in bxt_set_cdclk()
2199 _bxt_set_cdclk(display, cdclk_config, pipe); in bxt_set_cdclk()
2201 _bxt_set_cdclk(display, cdclk_config, pipe); in bxt_set_cdclk()
2204 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) in bxt_set_cdclk()
2205 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); in bxt_set_cdclk()
2207 if (DISPLAY_VER(display) >= 14) in bxt_set_cdclk()
2212 else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) in bxt_set_cdclk()
2213 ret = intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
2215 if (DISPLAY_VER(display) < 11) { in bxt_set_cdclk()
2222 ret = intel_pcode_write_timeout(display->drm, in bxt_set_cdclk()
2227 drm_err(display->drm, in bxt_set_cdclk()
2233 intel_update_cdclk(display); in bxt_set_cdclk()
2235 if (DISPLAY_VER(display) >= 11) in bxt_set_cdclk()
2240 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
2243 static void bxt_sanitize_cdclk(struct intel_display *display) in bxt_sanitize_cdclk() argument
2248 intel_update_cdclk(display); in bxt_sanitize_cdclk()
2249 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
2251 if (display->cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
2252 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in bxt_sanitize_cdclk()
2256 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2257 if (cdclk != display->cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2261 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_sanitize_cdclk()
2262 if (vco != display->cdclk.hw.vco) in bxt_sanitize_cdclk()
2270 cdctl = intel_de_read(display, CDCLK_CTL); in bxt_sanitize_cdclk()
2271 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); in bxt_sanitize_cdclk()
2278 cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); in bxt_sanitize_cdclk()
2279 expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); in bxt_sanitize_cdclk()
2286 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
2289 display->cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
2292 display->cdclk.hw.vco = ~0; in bxt_sanitize_cdclk()
2295 static void bxt_cdclk_init_hw(struct intel_display *display) in bxt_cdclk_init_hw() argument
2299 bxt_sanitize_cdclk(display); in bxt_cdclk_init_hw()
2301 if (display->cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2302 display->cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2305 cdclk_config = display->cdclk.hw; in bxt_cdclk_init_hw()
2312 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); in bxt_cdclk_init_hw()
2313 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2315 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2317 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); in bxt_cdclk_init_hw()
2320 static void bxt_cdclk_uninit_hw(struct intel_display *display) in bxt_cdclk_uninit_hw() argument
2322 struct intel_cdclk_config cdclk_config = display->cdclk.hw; in bxt_cdclk_uninit_hw()
2327 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
2329 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); in bxt_cdclk_uninit_hw()
2341 void intel_cdclk_init_hw(struct intel_display *display) in intel_cdclk_init_hw() argument
2343 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) in intel_cdclk_init_hw()
2344 bxt_cdclk_init_hw(display); in intel_cdclk_init_hw()
2345 else if (DISPLAY_VER(display) == 9) in intel_cdclk_init_hw()
2346 skl_cdclk_init_hw(display); in intel_cdclk_init_hw()
2356 void intel_cdclk_uninit_hw(struct intel_display *display) in intel_cdclk_uninit_hw() argument
2358 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) in intel_cdclk_uninit_hw()
2359 bxt_cdclk_uninit_hw(display); in intel_cdclk_uninit_hw()
2360 else if (DISPLAY_VER(display) == 9) in intel_cdclk_uninit_hw()
2361 skl_cdclk_uninit_hw(display); in intel_cdclk_uninit_hw()
2364 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, in intel_cdclk_can_crawl_and_squash() argument
2371 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); in intel_cdclk_can_crawl_and_squash()
2376 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) in intel_cdclk_can_crawl_and_squash()
2379 old_waveform = cdclk_squash_waveform(display, a->cdclk); in intel_cdclk_can_crawl_and_squash()
2380 new_waveform = cdclk_squash_waveform(display, b->cdclk); in intel_cdclk_can_crawl_and_squash()
2386 static bool intel_cdclk_can_crawl(struct intel_display *display, in intel_cdclk_can_crawl() argument
2392 if (!HAS_CDCLK_CRAWL(display)) in intel_cdclk_can_crawl()
2408 static bool intel_cdclk_can_squash(struct intel_display *display, in intel_cdclk_can_squash() argument
2418 if (!HAS_CDCLK_SQUASH(display)) in intel_cdclk_can_squash()
2455 static bool intel_cdclk_can_cd2x_update(struct intel_display *display, in intel_cdclk_can_cd2x_update() argument
2460 if (DISPLAY_VER(display) < 10 && !display->platform.broxton) in intel_cdclk_can_cd2x_update()
2469 if (HAS_CDCLK_SQUASH(display)) in intel_cdclk_can_cd2x_update()
2493 void intel_cdclk_dump_config(struct intel_display *display, in intel_cdclk_dump_config() argument
2497 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", in intel_cdclk_dump_config()
2503 static void intel_pcode_notify(struct intel_display *display, in intel_pcode_notify() argument
2513 if (!display->platform.dg2) in intel_pcode_notify()
2524 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, in intel_pcode_notify()
2530 drm_err(display->drm, in intel_pcode_notify()
2535 static void intel_set_cdclk(struct intel_display *display, in intel_set_cdclk() argument
2541 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) in intel_set_cdclk()
2544 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2547 intel_cdclk_dump_config(display, cdclk_config, context); in intel_set_cdclk()
2549 for_each_intel_encoder_with_psr(display->drm, encoder) { in intel_set_cdclk()
2555 intel_audio_cdclk_change_pre(display); in intel_set_cdclk()
2562 mutex_lock(&display->gmbus.mutex); in intel_set_cdclk()
2563 for_each_intel_dp(display->drm, encoder) { in intel_set_cdclk()
2567 &display->gmbus.mutex); in intel_set_cdclk()
2570 intel_cdclk_set_cdclk(display, cdclk_config, pipe); in intel_set_cdclk()
2572 for_each_intel_dp(display->drm, encoder) { in intel_set_cdclk()
2577 mutex_unlock(&display->gmbus.mutex); in intel_set_cdclk()
2579 for_each_intel_encoder_with_psr(display->drm, encoder) { in intel_set_cdclk()
2585 intel_audio_cdclk_change_post(display); in intel_set_cdclk()
2587 if (drm_WARN(display->drm, in intel_set_cdclk()
2588 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), in intel_set_cdclk()
2590 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); in intel_set_cdclk()
2591 intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); in intel_set_cdclk()
2597 struct intel_display *display = to_intel_display(state); in intel_cdclk_pcode_pre_notify() local
2636 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_pre_notify()
2642 struct intel_display *display = to_intel_display(state); in intel_cdclk_pcode_post_notify() local
2673 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_post_notify()
2698 struct intel_display *display = to_intel_display(state); in intel_set_cdclk_pre_plane_update() local
2710 if (display->platform.dg2) in intel_set_cdclk_pre_plane_update()
2735 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_pre_plane_update()
2737 intel_set_cdclk(display, &cdclk_config, pipe, in intel_set_cdclk_pre_plane_update()
2751 struct intel_display *display = to_intel_display(state); in intel_set_cdclk_post_plane_update() local
2762 if (display->platform.dg2) in intel_set_cdclk_post_plane_update()
2771 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_post_plane_update()
2773 intel_set_cdclk(display, &new_cdclk_state->actual, pipe, in intel_set_cdclk_post_plane_update()
2778 static int intel_cdclk_ppc(struct intel_display *display, bool double_wide) in intel_cdclk_ppc() argument
2780 return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1; in intel_cdclk_ppc()
2784 static int intel_cdclk_guardband(struct intel_display *display) in intel_cdclk_guardband() argument
2786 if (DISPLAY_VER(display) >= 9 || in intel_cdclk_guardband()
2787 display->platform.broadwell || display->platform.haswell) in intel_cdclk_guardband()
2789 else if (display->platform.cherryview) in intel_cdclk_guardband()
2797 struct intel_display *display = to_intel_display(crtc_state); in intel_pixel_rate_to_cdclk() local
2798 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); in intel_pixel_rate_to_cdclk()
2799 int guardband = intel_cdclk_guardband(display); in intel_pixel_rate_to_cdclk()
2808 struct intel_display *display = to_intel_display(crtc); in intel_planes_min_cdclk() local
2812 for_each_intel_plane_on_crtc(display->drm, crtc, plane) in intel_planes_min_cdclk()
2837 struct intel_display *display = to_intel_display(state); in intel_compute_min_cdclk() local
2865 min_cdclk = intel_bw_min_cdclk(display, bw_state); in intel_compute_min_cdclk()
2880 for_each_pipe(display, pipe) in intel_compute_min_cdclk()
2891 if (display->platform.geminilake && cdclk_state->active_pipes && in intel_compute_min_cdclk()
2895 if (min_cdclk > display->cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2896 drm_dbg_kms(display->drm, in intel_compute_min_cdclk()
2898 min_cdclk, display->cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2920 struct intel_display *display = to_intel_display(state); in bxt_compute_min_voltage_level() local
2948 for_each_pipe(display, pipe) in bxt_compute_min_voltage_level()
2957 struct intel_display *display = to_intel_display(state); in vlv_modeset_calc_cdclk() local
2966 cdclk = vlv_calc_cdclk(display, min_cdclk); in vlv_modeset_calc_cdclk()
2970 vlv_calc_voltage_level(display, cdclk); in vlv_modeset_calc_cdclk()
2973 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2977 vlv_calc_voltage_level(display, cdclk); in vlv_modeset_calc_cdclk()
3016 struct intel_display *display = to_intel_display(state); in skl_dpll0_vco() local
3025 vco = display->cdclk.skl_preferred_vco_freq; in skl_dpll0_vco()
3087 struct intel_display *display = to_intel_display(state); in bxt_modeset_calc_cdclk() local
3100 cdclk = bxt_calc_cdclk(display, min_cdclk); in bxt_modeset_calc_cdclk()
3101 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_modeset_calc_cdclk()
3107 intel_cdclk_calc_voltage_level(display, cdclk)); in bxt_modeset_calc_cdclk()
3110 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
3111 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_modeset_calc_cdclk()
3116 intel_cdclk_calc_voltage_level(display, cdclk); in bxt_modeset_calc_cdclk()
3168 struct intel_display *display = to_intel_display(state); in intel_atomic_get_cdclk_state() local
3171 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); in intel_atomic_get_cdclk_state()
3227 int intel_cdclk_init(struct intel_display *display) in intel_cdclk_init() argument
3235 intel_atomic_global_obj_init(display, &display->cdclk.obj, in intel_cdclk_init()
3241 static bool intel_cdclk_need_serialize(struct intel_display *display, in intel_cdclk_need_serialize() argument
3253 return cdclk_changed || (display->platform.dg2 && power_well_cnt_changed); in intel_cdclk_need_serialize()
3258 struct intel_display *display = to_intel_display(state); in intel_modeset_calc_cdclk() local
3277 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { in intel_modeset_calc_cdclk()
3297 intel_cdclk_can_cd2x_update(display, in intel_modeset_calc_cdclk()
3304 crtc = intel_crtc_for_pipe(display, pipe); in intel_modeset_calc_cdclk()
3314 if (intel_cdclk_can_crawl_and_squash(display, in intel_modeset_calc_cdclk()
3317 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3319 } else if (intel_cdclk_can_squash(display, in intel_modeset_calc_cdclk()
3322 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3324 } else if (intel_cdclk_can_crawl(display, in intel_modeset_calc_cdclk()
3327 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3332 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3344 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3348 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != in intel_modeset_calc_cdclk()
3349 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3350 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); in intel_modeset_calc_cdclk()
3357 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3361 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3369 void intel_cdclk_update_hw_state(struct intel_display *display) in intel_cdclk_update_hw_state() argument
3372 to_intel_bw_state(display->bw.obj.state); in intel_cdclk_update_hw_state()
3374 to_intel_cdclk_state(display->cdclk.obj.state); in intel_cdclk_update_hw_state()
3379 for_each_intel_crtc(display->drm, crtc) { in intel_cdclk_update_hw_state()
3391 cdclk_state->bw_min_cdclk = intel_bw_min_cdclk(display, bw_state); in intel_cdclk_update_hw_state()
3396 struct intel_display *display = to_intel_display(crtc); in intel_cdclk_crtc_disable_noatomic() local
3398 intel_cdclk_update_hw_state(display); in intel_cdclk_crtc_disable_noatomic()
3401 static int intel_compute_max_dotclk(struct intel_display *display) in intel_compute_max_dotclk() argument
3403 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); in intel_compute_max_dotclk()
3404 int guardband = intel_cdclk_guardband(display); in intel_compute_max_dotclk()
3405 int max_cdclk_freq = display->cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
3418 void intel_update_max_cdclk(struct intel_display *display) in intel_update_max_cdclk() argument
3420 if (DISPLAY_VERx100(display) >= 3002) { in intel_update_max_cdclk()
3421 display->cdclk.max_cdclk_freq = 480000; in intel_update_max_cdclk()
3422 } else if (DISPLAY_VER(display) >= 30) { in intel_update_max_cdclk()
3423 display->cdclk.max_cdclk_freq = 691200; in intel_update_max_cdclk()
3424 } else if (display->platform.jasperlake || display->platform.elkhartlake) { in intel_update_max_cdclk()
3425 if (display->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3426 display->cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
3428 display->cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
3429 } else if (DISPLAY_VER(display) >= 11) { in intel_update_max_cdclk()
3430 if (display->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3431 display->cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
3433 display->cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
3434 } else if (display->platform.geminilake) { in intel_update_max_cdclk()
3435 display->cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
3436 } else if (display->platform.broxton) { in intel_update_max_cdclk()
3437 display->cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3438 } else if (DISPLAY_VER(display) == 9) { in intel_update_max_cdclk()
3439 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; in intel_update_max_cdclk()
3442 vco = display->cdclk.skl_preferred_vco_freq; in intel_update_max_cdclk()
3443 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
3459 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3460 } else if (display->platform.broadwell) { in intel_update_max_cdclk()
3467 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) in intel_update_max_cdclk()
3468 display->cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3469 else if (display->platform.broadwell_ulx) in intel_update_max_cdclk()
3470 display->cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3471 else if (display->platform.broadwell_ult) in intel_update_max_cdclk()
3472 display->cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3474 display->cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3475 } else if (display->platform.cherryview) { in intel_update_max_cdclk()
3476 display->cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3477 } else if (display->platform.valleyview) { in intel_update_max_cdclk()
3478 display->cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3481 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; in intel_update_max_cdclk()
3484 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); in intel_update_max_cdclk()
3486 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", in intel_update_max_cdclk()
3487 display->cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3489 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", in intel_update_max_cdclk()
3490 display->cdclk.max_dotclk_freq); in intel_update_max_cdclk()
3499 void intel_update_cdclk(struct intel_display *display) in intel_update_cdclk() argument
3501 intel_cdclk_get_cdclk(display, &display->cdclk.hw); in intel_update_cdclk()
3509 if (display->platform.valleyview || display->platform.cherryview) in intel_update_cdclk()
3510 intel_de_write(display, GMBUSFREQ_VLV, in intel_update_cdclk()
3511 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3514 static int dg1_rawclk(struct intel_display *display) in dg1_rawclk() argument
3520 intel_de_write(display, PCH_RAWCLK_FREQ, in dg1_rawclk()
3526 static int cnp_rawclk(struct intel_display *display) in cnp_rawclk() argument
3531 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { in cnp_rawclk()
3547 if (INTEL_PCH_TYPE(display) >= PCH_ICP) in cnp_rawclk()
3551 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); in cnp_rawclk()
3555 static int pch_rawclk(struct intel_display *display) in pch_rawclk() argument
3557 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; in pch_rawclk()
3560 static int vlv_hrawclk(struct intel_display *display) in vlv_hrawclk() argument
3563 return vlv_get_cck_clock_hpll(display->drm, "hrawclk", in vlv_hrawclk()
3567 static int i9xx_hrawclk(struct intel_display *display) in i9xx_hrawclk() argument
3569 struct drm_i915_private *i915 = to_i915(display->drm); in i9xx_hrawclk()
3582 u32 intel_read_rawclk(struct intel_display *display) in intel_read_rawclk() argument
3586 if (INTEL_PCH_TYPE(display) >= PCH_MTL) in intel_read_rawclk()
3593 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) in intel_read_rawclk()
3594 freq = dg1_rawclk(display); in intel_read_rawclk()
3595 else if (INTEL_PCH_TYPE(display) >= PCH_CNP) in intel_read_rawclk()
3596 freq = cnp_rawclk(display); in intel_read_rawclk()
3597 else if (HAS_PCH_SPLIT(display)) in intel_read_rawclk()
3598 freq = pch_rawclk(display); in intel_read_rawclk()
3599 else if (display->platform.valleyview || display->platform.cherryview) in intel_read_rawclk()
3600 freq = vlv_hrawclk(display); in intel_read_rawclk()
3601 else if (DISPLAY_VER(display) >= 3) in intel_read_rawclk()
3602 freq = i9xx_hrawclk(display); in intel_read_rawclk()
3612 struct intel_display *display = m->private; in i915_cdclk_info_show() local
3614 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); in i915_cdclk_info_show()
3615 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); in i915_cdclk_info_show()
3616 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); in i915_cdclk_info_show()
3623 void intel_cdclk_debugfs_register(struct intel_display *display) in intel_cdclk_debugfs_register() argument
3625 struct drm_minor *minor = display->drm->primary; in intel_cdclk_debugfs_register()
3628 display, &i915_cdclk_info_fops); in intel_cdclk_debugfs_register()
3778 void intel_init_cdclk_hooks(struct intel_display *display) in intel_init_cdclk_hooks() argument
3780 if (DISPLAY_VER(display) >= 30) { in intel_init_cdclk_hooks()
3781 display->funcs.cdclk = &xe3lpd_cdclk_funcs; in intel_init_cdclk_hooks()
3782 display->cdclk.table = xe3lpd_cdclk_table; in intel_init_cdclk_hooks()
3783 } else if (DISPLAY_VER(display) >= 20) { in intel_init_cdclk_hooks()
3784 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3785 display->cdclk.table = xe2lpd_cdclk_table; in intel_init_cdclk_hooks()
3786 } else if (DISPLAY_VERx100(display) >= 1401) { in intel_init_cdclk_hooks()
3787 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3788 display->cdclk.table = xe2hpd_cdclk_table; in intel_init_cdclk_hooks()
3789 } else if (DISPLAY_VER(display) >= 14) { in intel_init_cdclk_hooks()
3790 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3791 display->cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3792 } else if (display->platform.dg2) { in intel_init_cdclk_hooks()
3793 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3794 display->cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3795 } else if (display->platform.alderlake_p) { in intel_init_cdclk_hooks()
3797 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { in intel_init_cdclk_hooks()
3798 display->cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3799 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3800 } else if (display->platform.alderlake_p_raptorlake_u) { in intel_init_cdclk_hooks()
3801 display->cdclk.table = rplu_cdclk_table; in intel_init_cdclk_hooks()
3802 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3804 display->cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3805 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3807 } else if (display->platform.rocketlake) { in intel_init_cdclk_hooks()
3808 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3809 display->cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3810 } else if (DISPLAY_VER(display) >= 12) { in intel_init_cdclk_hooks()
3811 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3812 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3813 } else if (display->platform.jasperlake || display->platform.elkhartlake) { in intel_init_cdclk_hooks()
3814 display->funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3815 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3816 } else if (DISPLAY_VER(display) >= 11) { in intel_init_cdclk_hooks()
3817 display->funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3818 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3819 } else if (display->platform.geminilake || display->platform.broxton) { in intel_init_cdclk_hooks()
3820 display->funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3821 if (display->platform.geminilake) in intel_init_cdclk_hooks()
3822 display->cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3824 display->cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3825 } else if (DISPLAY_VER(display) == 9) { in intel_init_cdclk_hooks()
3826 display->funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3827 } else if (display->platform.broadwell) { in intel_init_cdclk_hooks()
3828 display->funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3829 } else if (display->platform.haswell) { in intel_init_cdclk_hooks()
3830 display->funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3831 } else if (display->platform.cherryview) { in intel_init_cdclk_hooks()
3832 display->funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3833 } else if (display->platform.valleyview) { in intel_init_cdclk_hooks()
3834 display->funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3835 } else if (display->platform.sandybridge || display->platform.ivybridge) { in intel_init_cdclk_hooks()
3836 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3837 } else if (display->platform.ironlake) { in intel_init_cdclk_hooks()
3838 display->funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3839 } else if (display->platform.gm45) { in intel_init_cdclk_hooks()
3840 display->funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3841 } else if (display->platform.g45) { in intel_init_cdclk_hooks()
3842 display->funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3843 } else if (display->platform.i965gm) { in intel_init_cdclk_hooks()
3844 display->funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3845 } else if (display->platform.i965g) { in intel_init_cdclk_hooks()
3846 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3847 } else if (display->platform.pineview) { in intel_init_cdclk_hooks()
3848 display->funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3849 } else if (display->platform.g33) { in intel_init_cdclk_hooks()
3850 display->funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3851 } else if (display->platform.i945gm) { in intel_init_cdclk_hooks()
3852 display->funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3853 } else if (display->platform.i945g) { in intel_init_cdclk_hooks()
3854 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3855 } else if (display->platform.i915gm) { in intel_init_cdclk_hooks()
3856 display->funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3857 } else if (display->platform.i915g) { in intel_init_cdclk_hooks()
3858 display->funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3859 } else if (display->platform.i865g) { in intel_init_cdclk_hooks()
3860 display->funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3861 } else if (display->platform.i85x) { in intel_init_cdclk_hooks()
3862 display->funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3863 } else if (display->platform.i845g) { in intel_init_cdclk_hooks()
3864 display->funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3865 } else if (display->platform.i830) { in intel_init_cdclk_hooks()
3866 display->funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3869 if (drm_WARN(display->drm, !display->funcs.cdclk, in intel_init_cdclk_hooks()
3871 display->funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3919 void intel_cdclk_read_hw(struct intel_display *display) in intel_cdclk_read_hw() argument
3923 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); in intel_cdclk_read_hw()
3925 intel_update_cdclk(display); in intel_cdclk_read_hw()
3926 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in intel_cdclk_read_hw()
3927 cdclk_state->actual = display->cdclk.hw; in intel_cdclk_read_hw()
3928 cdclk_state->logical = display->cdclk.hw; in intel_cdclk_read_hw()