Lines Matching refs:DISPLAY_VER
415 if (DISPLAY_VER(display) >= 4) { in intel_wait_for_pipe_off()
516 if (DISPLAY_VER(display) == 13) in intel_enable_transcoder()
520 if (DISPLAY_VER(display) >= 14) { in intel_enable_transcoder()
524 if (DISPLAY_VER(display) == 14) in intel_enable_transcoder()
539 if (DISPLAY_VER(display) >= 13 && in intel_enable_transcoder()
593 if (DISPLAY_VER(display) >= 13 && in intel_disable_transcoder()
599 if (DISPLAY_VER(display) >= 12) in intel_disable_transcoder()
709 if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes) in intel_plane_disable_noatomic()
756 else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30)) in icl_set_pipe_chicken()
841 if (DISPLAY_VER(display) == 9) in needs_nv12_wa()
852 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11) in needs_scalerclk_wa()
865 DISPLAY_VER(display) == 11) in needs_cursorclk_wa()
874 if (DISPLAY_VER(display) == 9) { in intel_async_flip_vtd_wa()
896 (DISPLAY_VER(display) == 9 || display->platform.broadwell || in needs_async_flip_vtd_wa()
1275 if (DISPLAY_VER(display) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) in intel_pre_plane_update()
1591 return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled; in glk_need_scaler_clock_gating_wa()
1688 if (DISPLAY_VER(display) >= 9 || display->platform.broadwell) in hsw_crtc_enable()
1704 if (DISPLAY_VER(display) >= 9) in hsw_crtc_enable()
1717 if (DISPLAY_VER(display) >= 11) in hsw_crtc_enable()
1846 if (DISPLAY_VER(display) >= 13) in intel_phy_is_tc()
1869 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) in intel_port_to_phy()
1871 else if (DISPLAY_VER(display) >= 13 && port >= PORT_TC1) in intel_port_to_phy()
1890 if (DISPLAY_VER(display) >= 12) in intel_port_to_tc()
2096 if (DISPLAY_VER(display) != 2) in i9xx_crtc_enable()
2116 if (DISPLAY_VER(display) == 2) in i9xx_crtc_enable()
2132 if (DISPLAY_VER(display) == 2) in i9xx_crtc_disable()
2156 if (DISPLAY_VER(display) != 2) in i9xx_crtc_disable()
2393 if (DISPLAY_VER(display) < 4) { in intel_crtc_compute_pipe_mode()
2598 if (DISPLAY_VER(display) >= 5) in intel_cpu_transcoder_set_m1_n1()
2672 if (DISPLAY_VER(display) >= 13) { in intel_set_transcoder_timings()
2684 if (DISPLAY_VER(display) >= 4) in intel_set_transcoder_timings()
2728 if (DISPLAY_VER(display) >= 30) { in intel_set_transcoder_timings()
2762 if (DISPLAY_VER(display) >= 13) { in intel_set_transcoder_timings_lrr()
2822 if (DISPLAY_VER(display) == 2) in intel_pipe_is_interlaced()
2825 if (DISPLAY_VER(display) >= 9 || in intel_pipe_is_interlaced()
2878 if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) in intel_get_transcoder_timings()
2884 if (DISPLAY_VER(display) >= 30) in intel_get_transcoder_timings()
2964 if (DISPLAY_VER(display) < 4 || in i9xx_set_pipeconf()
3002 if (DISPLAY_VER(display) < 30) in bdw_get_pipe_misc_output_format()
3080 if (DISPLAY_VER(display) >= 4) { in i9xx_get_pipe_config()
3232 if (DISPLAY_VER(display) >= 13) in bdw_set_pipe_misc()
3248 val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE : in bdw_set_pipe_misc()
3251 if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state)) in bdw_set_pipe_misc()
3254 if (DISPLAY_VER(display) >= 12) in bdw_set_pipe_misc()
3289 if (DISPLAY_VER(display) >= 13) in bdw_get_pipe_misc_bpp()
3328 if (DISPLAY_VER(display) >= 5) in intel_cpu_transcoder_get_m1_n1()
3438 if (DISPLAY_VER(display) >= 12) in joiner_pipes()
3440 else if (DISPLAY_VER(display) >= 11) in joiner_pipes()
3718 if (DISPLAY_VER(display) >= 11) in hsw_panel_transcoders()
3950 DISPLAY_VER(display) >= 11) in hsw_get_pipe_config()
3983 if (DISPLAY_VER(display) >= 9) in hsw_get_pipe_config()
4206 if (DISPLAY_VER(display) >= 9) in hsw_compute_linetime_wm()
4232 if (DISPLAY_VER(display) < 5 && !display->platform.g4x && in intel_crtc_atomic_check()
4255 if (DISPLAY_VER(display) >= 9) { in intel_crtc_atomic_check()
4274 if (DISPLAY_VER(display) >= 9 || in intel_crtc_atomic_check()
4341 else if (DISPLAY_VER(display) >= 5) in intel_display_max_pipe_bpp()
5281 if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) || in intel_pipe_config_compare()
5298 if (DISPLAY_VER(display) < 4) in intel_pipe_config_compare()
5346 if (DISPLAY_VER(display) >= 14) in intel_pipe_config_compare()
5352 if (display->platform.g4x || DISPLAY_VER(display) >= 5) in intel_pipe_config_compare()
6555 if (DISPLAY_VER(display) != 2 || crtc_state->active_planes) in intel_crtc_arm_fifo_underrun()
6583 if (DISPLAY_VER(display) >= 9) { in intel_pipe_fastset()
6601 if (DISPLAY_VER(display) >= 9 || in intel_pipe_fastset()
6633 if (DISPLAY_VER(display) >= 9 || display->platform.broadwell) in commit_pipe_pre_planes()
6660 if (DISPLAY_VER(display) >= 9 && !modeset) in commit_pipe_post_planes()
6727 if (DISPLAY_VER(display) >= 11 && in intel_pre_update_crtc()
7215 (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) && in intel_atomic_dsb_prepare()
7281 if (DISPLAY_VER(display) >= 9) in intel_atomic_dsb_finish()
7474 if (DISPLAY_VER(display) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) in intel_atomic_commit_tail()
7624 if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) { in intel_atomic_commit()
7711 if (DISPLAY_VER(display) >= 9) in intel_ddi_crt_present()
7886 } else if (DISPLAY_VER(display) == 2) { in intel_setup_outputs()
7962 if (DISPLAY_VER(display) >= 11) { in intel_mode_valid()
7967 } else if (DISPLAY_VER(display) >= 9 || in intel_mode_valid()
7973 } else if (DISPLAY_VER(display) >= 3) { in intel_mode_valid()
8007 if (DISPLAY_VER(display) >= 5) { in intel_cpu_transcoder_mode_valid()
8026 if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) && in intel_cpu_transcoder_mode_valid()
8044 if (DISPLAY_VER(display) < 9) in intel_mode_valid_max_plane_size()
8052 if (DISPLAY_VER(display) >= 30) { in intel_mode_valid_max_plane_size()
8055 } else if (DISPLAY_VER(display) >= 11) { in intel_mode_valid_max_plane_size()
8123 if (DISPLAY_VER(display) >= 9) { in intel_init_display_hooks()