Lines Matching refs:display
65 struct intel_display *display; member
87 static struct intel_dmc *display_to_dmc(struct intel_display *display) in display_to_dmc() argument
89 return display->dmc.dmc; in display_to_dmc()
92 static const char *dmc_firmware_param(struct intel_display *display) in dmc_firmware_param() argument
94 const char *p = display->params.dmc_firmware_path; in dmc_firmware_param()
99 static bool dmc_firmware_param_disabled(struct intel_display *display) in dmc_firmware_param_disabled() argument
101 const char *p = dmc_firmware_param(display); in dmc_firmware_param_disabled()
182 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) in dmc_firmware_default() argument
187 if (DISPLAY_VERx100(display) == 3002 || in dmc_firmware_default()
188 DISPLAY_VERx100(display) == 3000) { in dmc_firmware_default()
191 } else if (DISPLAY_VERx100(display) == 2000) { in dmc_firmware_default()
194 } else if (DISPLAY_VERx100(display) == 1401) { in dmc_firmware_default()
197 } else if (DISPLAY_VERx100(display) == 1400) { in dmc_firmware_default()
200 } else if (display->platform.dg2) { in dmc_firmware_default()
203 } else if (display->platform.alderlake_p) { in dmc_firmware_default()
206 } else if (display->platform.alderlake_s) { in dmc_firmware_default()
209 } else if (display->platform.dg1) { in dmc_firmware_default()
212 } else if (display->platform.rocketlake) { in dmc_firmware_default()
215 } else if (display->platform.tigerlake) { in dmc_firmware_default()
218 } else if (DISPLAY_VER(display) == 11) { in dmc_firmware_default()
221 } else if (display->platform.geminilake) { in dmc_firmware_default()
224 } else if (display->platform.kabylake || in dmc_firmware_default()
225 display->platform.coffeelake || in dmc_firmware_default()
226 display->platform.cometlake) { in dmc_firmware_default()
229 } else if (display->platform.skylake) { in dmc_firmware_default()
232 } else if (display->platform.broxton) { in dmc_firmware_default()
399 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) in has_dmc_id_fw() argument
401 struct intel_dmc *dmc = display_to_dmc(display); in has_dmc_id_fw()
406 bool intel_dmc_has_payload(struct intel_display *display) in intel_dmc_has_payload() argument
408 return has_dmc_id_fw(display, DMC_FW_MAIN); in intel_dmc_has_payload()
412 intel_get_stepping_info(struct intel_display *display, in intel_get_stepping_info() argument
415 const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display)); in intel_get_stepping_info()
422 static void gen9_set_dc_state_debugmask(struct intel_display *display) in gen9_set_dc_state_debugmask() argument
425 intel_de_rmw(display, DC_STATE_DEBUG, 0, in gen9_set_dc_state_debugmask()
427 intel_de_posting_read(display, DC_STATE_DEBUG); in gen9_set_dc_state_debugmask()
430 static void disable_event_handler(struct intel_display *display, in disable_event_handler() argument
433 intel_de_write(display, ctl_reg, in disable_event_handler()
438 intel_de_write(display, htp_reg, 0); in disable_event_handler()
441 static void disable_all_event_handlers(struct intel_display *display, in disable_all_event_handlers() argument
447 if (DISPLAY_VER(display) < 12) in disable_all_event_handlers()
450 if (!has_dmc_id_fw(display, dmc_id)) in disable_all_event_handlers()
454 disable_event_handler(display, in disable_all_event_handlers()
455 DMC_EVT_CTL(display, dmc_id, handler), in disable_all_event_handlers()
456 DMC_EVT_HTP(display, dmc_id, handler)); in disable_all_event_handlers()
459 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable) in adlp_pipedmc_clock_gating_wa() argument
472 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), in adlp_pipedmc_clock_gating_wa()
476 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), in adlp_pipedmc_clock_gating_wa()
480 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) in mtl_pipedmc_clock_gating_wa() argument
487 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, in mtl_pipedmc_clock_gating_wa()
492 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) in pipedmc_clock_gating_wa() argument
494 if (display->platform.meteorlake && enable) in pipedmc_clock_gating_wa()
495 mtl_pipedmc_clock_gating_wa(display); in pipedmc_clock_gating_wa()
496 else if (DISPLAY_VER(display) == 13) in pipedmc_clock_gating_wa()
497 adlp_pipedmc_clock_gating_wa(display, enable); in pipedmc_clock_gating_wa()
500 static u32 pipedmc_interrupt_mask(struct intel_display *display) in pipedmc_interrupt_mask() argument
520 static bool is_dmc_evt_ctl_reg(struct intel_display *display, in is_dmc_evt_ctl_reg() argument
524 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); in is_dmc_evt_ctl_reg()
525 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); in is_dmc_evt_ctl_reg()
530 static bool is_dmc_evt_htp_reg(struct intel_display *display, in is_dmc_evt_htp_reg() argument
534 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); in is_dmc_evt_htp_reg()
535 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); in is_dmc_evt_htp_reg()
540 static bool is_event_handler(struct intel_display *display, in is_event_handler() argument
545 return is_dmc_evt_ctl_reg(display, dmc_id, reg) && in is_event_handler()
549 static bool disable_dmc_evt(struct intel_display *display, in disable_dmc_evt() argument
553 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) in disable_dmc_evt()
561 if (display->platform.tigerlake && in disable_dmc_evt()
562 is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data)) in disable_dmc_evt()
566 if ((display->platform.tigerlake || display->platform.alderlake_s) && in disable_dmc_evt()
567 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg, data)) in disable_dmc_evt()
573 static u32 dmc_mmiodata(struct intel_display *display, in dmc_mmiodata() argument
577 if (disable_dmc_evt(display, dmc_id, in dmc_mmiodata()
585 static void dmc_load_mmio(struct intel_display *display, enum intel_dmc_id dmc_id) in dmc_load_mmio() argument
587 struct intel_dmc *dmc = display_to_dmc(display); in dmc_load_mmio()
591 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], in dmc_load_mmio()
592 dmc_mmiodata(display, dmc, dmc_id, i)); in dmc_load_mmio()
596 static void dmc_load_program(struct intel_display *display, enum intel_dmc_id dmc_id) in dmc_load_program() argument
598 struct intel_dmc *dmc = display_to_dmc(display); in dmc_load_program()
601 disable_all_event_handlers(display, dmc_id); in dmc_load_program()
606 intel_de_write_fw(display, in dmc_load_program()
613 dmc_load_mmio(display, dmc_id); in dmc_load_program()
616 static void assert_dmc_loaded(struct intel_display *display, in assert_dmc_loaded() argument
619 struct intel_dmc *dmc = display_to_dmc(display); in assert_dmc_loaded()
623 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) in assert_dmc_loaded()
626 found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0)); in assert_dmc_loaded()
629 drm_WARN(display->drm, found != expected, in assert_dmc_loaded()
636 found = intel_de_read(display, reg); in assert_dmc_loaded()
637 expected = dmc_mmiodata(display, dmc, dmc_id, i); in assert_dmc_loaded()
640 if (is_dmc_evt_ctl_reg(display, dmc_id, reg)) { in assert_dmc_loaded()
645 drm_WARN(display->drm, found != expected, in assert_dmc_loaded()
651 void assert_main_dmc_loaded(struct intel_display *display) in assert_main_dmc_loaded() argument
653 assert_dmc_loaded(display, DMC_FW_MAIN); in assert_main_dmc_loaded()
656 static bool need_pipedmc_load_program(struct intel_display *display) in need_pipedmc_load_program() argument
659 return DISPLAY_VER(display) == 12; in need_pipedmc_load_program()
662 static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe) in need_pipedmc_load_mmio() argument
669 if (DISPLAY_VER(display) == 30) in need_pipedmc_load_mmio()
678 if (DISPLAY_VER(display) == 20) in need_pipedmc_load_mmio()
685 if (display->platform.battlemage) in need_pipedmc_load_mmio()
694 if (display->platform.dg2) in need_pipedmc_load_mmio()
702 if (IS_DISPLAY_VER(display, 13, 14)) in need_pipedmc_load_mmio()
710 struct intel_display *display = to_intel_display(crtc_state); in can_enable_pipedmc() local
717 if (DISPLAY_VER(display) == 12 && crtc_state->has_psr) in can_enable_pipedmc()
725 struct intel_display *display = to_intel_display(crtc_state); in intel_dmc_enable_pipe() local
730 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) in intel_dmc_enable_pipe()
738 if (need_pipedmc_load_program(display)) in intel_dmc_enable_pipe()
739 dmc_load_program(display, dmc_id); in intel_dmc_enable_pipe()
740 else if (need_pipedmc_load_mmio(display, pipe)) in intel_dmc_enable_pipe()
741 dmc_load_mmio(display, dmc_id); in intel_dmc_enable_pipe()
743 assert_dmc_loaded(display, dmc_id); in intel_dmc_enable_pipe()
745 if (DISPLAY_VER(display) >= 20) { in intel_dmc_enable_pipe()
746 intel_flipq_reset(display, pipe); in intel_dmc_enable_pipe()
748 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); in intel_dmc_enable_pipe()
749 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display)); in intel_dmc_enable_pipe()
752 if (DISPLAY_VER(display) >= 14) in intel_dmc_enable_pipe()
753 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); in intel_dmc_enable_pipe()
755 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); in intel_dmc_enable_pipe()
760 struct intel_display *display = to_intel_display(crtc_state); in intel_dmc_disable_pipe() local
765 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) in intel_dmc_disable_pipe()
768 if (DISPLAY_VER(display) >= 14) in intel_dmc_disable_pipe()
769 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); in intel_dmc_disable_pipe()
771 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); in intel_dmc_disable_pipe()
773 if (DISPLAY_VER(display) >= 20) { in intel_dmc_disable_pipe()
774 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0); in intel_dmc_disable_pipe()
775 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); in intel_dmc_disable_pipe()
777 intel_flipq_reset(display, pipe); in intel_dmc_disable_pipe()
781 static void dmc_configure_event(struct intel_display *display, in dmc_configure_event() argument
786 struct intel_dmc *dmc = display_to_dmc(display); in dmc_configure_event()
794 if (!is_event_handler(display, dmc_id, event_id, reg, data)) in dmc_configure_event()
797 intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable()); in dmc_configure_event()
801 drm_WARN_ONCE(display->drm, num_handlers != 1, in dmc_configure_event()
815 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, in intel_dmc_block_pkgc() argument
818 intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe), in intel_dmc_block_pkgc()
833 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, in intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() argument
838 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable); in intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank()
849 void intel_dmc_load_program(struct intel_display *display) in intel_dmc_load_program() argument
851 struct i915_power_domains *power_domains = &display->power.domains; in intel_dmc_load_program()
854 if (!intel_dmc_has_payload(display)) in intel_dmc_load_program()
857 assert_display_rpm_held(display); in intel_dmc_load_program()
859 pipedmc_clock_gating_wa(display, true); in intel_dmc_load_program()
862 dmc_load_program(display, dmc_id); in intel_dmc_load_program()
863 assert_dmc_loaded(display, dmc_id); in intel_dmc_load_program()
866 if (DISPLAY_VER(display) >= 20) in intel_dmc_load_program()
867 intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL, in intel_dmc_load_program()
875 gen9_set_dc_state_debugmask(display); in intel_dmc_load_program()
877 pipedmc_clock_gating_wa(display, false); in intel_dmc_load_program()
887 void intel_dmc_disable_program(struct intel_display *display) in intel_dmc_disable_program() argument
891 if (!intel_dmc_has_payload(display)) in intel_dmc_disable_program()
894 pipedmc_clock_gating_wa(display, true); in intel_dmc_disable_program()
897 disable_all_event_handlers(display, dmc_id); in intel_dmc_disable_program()
899 pipedmc_clock_gating_wa(display, false); in intel_dmc_disable_program()
929 struct intel_display *display = dmc->display; in dmc_set_fw_offset() local
937 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); in dmc_set_fw_offset()
959 struct intel_display *display = dmc->display; in dmc_mmio_addr_sanity_check() local
969 } else if (DISPLAY_VER(display) >= 13) { in dmc_mmio_addr_sanity_check()
972 } else if (DISPLAY_VER(display) >= 12) { in dmc_mmio_addr_sanity_check()
976 drm_warn(display->drm, "Unknown mmio range for sanity check"); in dmc_mmio_addr_sanity_check()
992 struct intel_display *display = dmc->display; in parse_dmc_fw_header() local
1040 drm_err(display->drm, "Unknown DMC fw header version: %u\n", in parse_dmc_fw_header()
1046 drm_err(display->drm, "DMC firmware has wrong dmc header length " in parse_dmc_fw_header()
1053 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); in parse_dmc_fw_header()
1059 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n"); in parse_dmc_fw_header()
1063 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); in parse_dmc_fw_header()
1068 drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", in parse_dmc_fw_header()
1070 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : in parse_dmc_fw_header()
1071 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", in parse_dmc_fw_header()
1072 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], in parse_dmc_fw_header()
1086 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size); in parse_dmc_fw_header()
1101 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); in parse_dmc_fw_header()
1111 struct intel_display *display = dmc->display; in parse_dmc_fw_package() local
1124 drm_err(display->drm, "DMC firmware has unknown header version %u\n", in parse_dmc_fw_package()
1138 drm_err(display->drm, "DMC firmware has wrong package header length " in parse_dmc_fw_package()
1156 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); in parse_dmc_fw_package()
1165 struct intel_display *display = dmc->display; in parse_dmc_fw_css() local
1168 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); in parse_dmc_fw_css()
1174 drm_err(display->drm, "DMC firmware has wrong CSS header length " in parse_dmc_fw_css()
1187 struct intel_display *display = dmc->display; in parse_dmc_fw() local
1192 const struct stepping_info *si = intel_get_stepping_info(display, &display_info); in parse_dmc_fw()
1222 drm_err(display->drm, "Reading beyond the fw_size\n"); in parse_dmc_fw()
1230 if (!intel_dmc_has_payload(display)) { in parse_dmc_fw()
1231 drm_err(display->drm, "DMC firmware main program not found\n"); in parse_dmc_fw()
1238 static void intel_dmc_runtime_pm_get(struct intel_display *display) in intel_dmc_runtime_pm_get() argument
1240 drm_WARN_ON(display->drm, display->dmc.wakeref); in intel_dmc_runtime_pm_get()
1241 display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); in intel_dmc_runtime_pm_get()
1244 static void intel_dmc_runtime_pm_put(struct intel_display *display) in intel_dmc_runtime_pm_put() argument
1247 fetch_and_zero(&display->dmc.wakeref); in intel_dmc_runtime_pm_put()
1249 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); in intel_dmc_runtime_pm_put()
1252 static const char *dmc_fallback_path(struct intel_display *display) in dmc_fallback_path() argument
1254 if (display->platform.alderlake_p) in dmc_fallback_path()
1263 struct intel_display *display = dmc->display; in dmc_load_work_fn() local
1268 err = request_firmware(&fw, dmc->fw_path, display->drm->dev); in dmc_load_work_fn()
1270 if (err == -ENOENT && !dmc_firmware_param(display)) { in dmc_load_work_fn()
1271 fallback_path = dmc_fallback_path(display); in dmc_load_work_fn()
1273 drm_dbg_kms(display->drm, "%s not found, falling back to %s\n", in dmc_load_work_fn()
1275 err = request_firmware(&fw, fallback_path, display->drm->dev); in dmc_load_work_fn()
1282 drm_notice(display->drm, in dmc_load_work_fn()
1285 drm_notice(display->drm, "DMC firmware homepage: %s", in dmc_load_work_fn()
1292 drm_notice(display->drm, in dmc_load_work_fn()
1298 intel_dmc_load_program(display); in dmc_load_work_fn()
1299 intel_dmc_runtime_pm_put(display); in dmc_load_work_fn()
1301 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n", in dmc_load_work_fn()
1316 void intel_dmc_init(struct intel_display *display) in intel_dmc_init() argument
1320 if (!HAS_DMC(display)) in intel_dmc_init()
1331 intel_dmc_runtime_pm_get(display); in intel_dmc_init()
1337 dmc->display = display; in intel_dmc_init()
1341 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); in intel_dmc_init()
1343 if (dmc_firmware_param_disabled(display)) { in intel_dmc_init()
1344 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n"); in intel_dmc_init()
1348 if (dmc_firmware_param(display)) in intel_dmc_init()
1349 dmc->fw_path = dmc_firmware_param(display); in intel_dmc_init()
1352 drm_dbg_kms(display->drm, in intel_dmc_init()
1357 display->dmc.dmc = dmc; in intel_dmc_init()
1359 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); in intel_dmc_init()
1360 queue_work(display->wq.unordered, &dmc->work); in intel_dmc_init()
1376 void intel_dmc_suspend(struct intel_display *display) in intel_dmc_suspend() argument
1378 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_suspend()
1380 if (!HAS_DMC(display)) in intel_dmc_suspend()
1387 if (!intel_dmc_has_payload(display)) in intel_dmc_suspend()
1388 intel_dmc_runtime_pm_put(display); in intel_dmc_suspend()
1391 void intel_dmc_wait_fw_load(struct intel_display *display) in intel_dmc_wait_fw_load() argument
1393 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_wait_fw_load()
1395 if (!HAS_DMC(display)) in intel_dmc_wait_fw_load()
1409 void intel_dmc_resume(struct intel_display *display) in intel_dmc_resume() argument
1411 if (!HAS_DMC(display)) in intel_dmc_resume()
1418 if (!intel_dmc_has_payload(display)) in intel_dmc_resume()
1419 intel_dmc_runtime_pm_get(display); in intel_dmc_resume()
1429 void intel_dmc_fini(struct intel_display *display) in intel_dmc_fini() argument
1431 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_fini()
1434 if (!HAS_DMC(display)) in intel_dmc_fini()
1437 intel_dmc_suspend(display); in intel_dmc_fini()
1438 drm_WARN_ON(display->drm, display->dmc.wakeref); in intel_dmc_fini()
1445 display->dmc.dmc = NULL; in intel_dmc_fini()
1455 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display) in intel_dmc_snapshot_capture() argument
1457 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_snapshot_capture()
1460 if (!HAS_DMC(display)) in intel_dmc_snapshot_capture()
1468 snapshot->loaded = intel_dmc_has_payload(display); in intel_dmc_snapshot_capture()
1488 void intel_dmc_update_dc6_allowed_count(struct intel_display *display, in intel_dmc_update_dc6_allowed_count() argument
1491 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_update_dc6_allowed_count()
1494 if (DISPLAY_VER(dmc->display) < 14) in intel_dmc_update_dc6_allowed_count()
1497 dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT); in intel_dmc_update_dc6_allowed_count()
1505 static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count) in intel_dmc_get_dc6_allowed_count() argument
1507 struct i915_power_domains *power_domains = &display->power.domains; in intel_dmc_get_dc6_allowed_count()
1508 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_get_dc6_allowed_count()
1511 if (DISPLAY_VER(display) < 14) in intel_dmc_get_dc6_allowed_count()
1515 dc6_enabled = intel_de_read(display, DC_STATE_EN) & in intel_dmc_get_dc6_allowed_count()
1518 intel_dmc_update_dc6_allowed_count(display, false); in intel_dmc_get_dc6_allowed_count()
1528 struct intel_display *display = m->private; in intel_dmc_debugfs_status_show() local
1529 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_debugfs_status_show()
1534 if (!HAS_DMC(display)) in intel_dmc_debugfs_status_show()
1537 wakeref = intel_display_rpm_get(display); in intel_dmc_debugfs_status_show()
1541 str_yes_no(intel_dmc_has_payload(display))); in intel_dmc_debugfs_status_show()
1544 str_yes_no(DISPLAY_VER(display) >= 12)); in intel_dmc_debugfs_status_show()
1546 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); in intel_dmc_debugfs_status_show()
1548 str_yes_no(display->platform.alderlake_p || in intel_dmc_debugfs_status_show()
1549 DISPLAY_VER(display) >= 14)); in intel_dmc_debugfs_status_show()
1551 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); in intel_dmc_debugfs_status_show()
1553 if (!intel_dmc_has_payload(display)) in intel_dmc_debugfs_status_show()
1559 if (DISPLAY_VER(display) >= 12) { in intel_dmc_debugfs_status_show()
1562 if (display->platform.dgfx || DISPLAY_VER(display) >= 14) { in intel_dmc_debugfs_status_show()
1572 intel_de_read(display, dc3co_reg)); in intel_dmc_debugfs_status_show()
1574 dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT : in intel_dmc_debugfs_status_show()
1576 if (!display->platform.geminilake && !display->platform.broxton) in intel_dmc_debugfs_status_show()
1580 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); in intel_dmc_debugfs_status_show()
1582 if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count)) in intel_dmc_debugfs_status_show()
1587 intel_de_read(display, dc6_reg)); in intel_dmc_debugfs_status_show()
1590 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); in intel_dmc_debugfs_status_show()
1594 intel_de_read(display, DMC_SSP_BASE)); in intel_dmc_debugfs_status_show()
1595 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); in intel_dmc_debugfs_status_show()
1597 intel_display_rpm_put(display, wakeref); in intel_dmc_debugfs_status_show()
1604 void intel_dmc_debugfs_register(struct intel_display *display) in intel_dmc_debugfs_register() argument
1606 struct drm_minor *minor = display->drm->primary; in intel_dmc_debugfs_register()
1609 display, &intel_dmc_debugfs_status_fops); in intel_dmc_debugfs_register()
1612 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe) in intel_pipedmc_irq_handler() argument
1614 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in intel_pipedmc_irq_handler()
1617 if (DISPLAY_VER(display) >= 20) { in intel_pipedmc_irq_handler()
1618 tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe)); in intel_pipedmc_irq_handler()
1619 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp); in intel_pipedmc_irq_handler()
1622 spin_lock(&display->drm->event_lock); in intel_pipedmc_irq_handler()
1635 spin_unlock(&display->drm->event_lock); in intel_pipedmc_irq_handler()
1639 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n", in intel_pipedmc_irq_handler()
1642 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC GTT fault\n", in intel_pipedmc_irq_handler()
1645 drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC error\n", in intel_pipedmc_irq_handler()
1649 int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK; in intel_pipedmc_irq_handler()
1651 drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt vector 0x%x\n", in intel_pipedmc_irq_handler()
1658 struct intel_display *display = to_intel_display(crtc); in intel_pipedmc_enable_event() local
1661 dmc_configure_event(display, dmc_id, event, true); in intel_pipedmc_enable_event()
1667 struct intel_display *display = to_intel_display(crtc); in intel_pipedmc_disable_event() local
1670 dmc_configure_event(display, dmc_id, event, false); in intel_pipedmc_disable_event()
1675 struct intel_display *display = to_intel_display(crtc); in intel_pipedmc_start_mmioaddr() local
1676 struct intel_dmc *dmc = display_to_dmc(display); in intel_pipedmc_start_mmioaddr()