Lines Matching refs:dmc
89 return display->dmc.dmc; in display_to_dmc()
401 struct intel_dmc *dmc = display_to_dmc(display); in has_dmc_id_fw() local
403 return dmc && dmc->dmc_info[dmc_id].payload; in has_dmc_id_fw()
574 struct intel_dmc *dmc, in dmc_mmiodata() argument
578 dmc->dmc_info[dmc_id].mmioaddr[i], in dmc_mmiodata()
579 dmc->dmc_info[dmc_id].mmiodata[i])) in dmc_mmiodata()
582 return dmc->dmc_info[dmc_id].mmiodata[i]; in dmc_mmiodata()
587 struct intel_dmc *dmc = display_to_dmc(display); in dmc_load_mmio() local
590 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { in dmc_load_mmio()
591 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], in dmc_load_mmio()
592 dmc_mmiodata(display, dmc, dmc_id, i)); in dmc_load_mmio()
598 struct intel_dmc *dmc = display_to_dmc(display); in dmc_load_program() local
605 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { in dmc_load_program()
607 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), in dmc_load_program()
608 dmc->dmc_info[dmc_id].payload[i]); in dmc_load_program()
619 struct intel_dmc *dmc = display_to_dmc(display); in assert_dmc_loaded() local
626 found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0)); in assert_dmc_loaded()
627 expected = dmc->dmc_info[dmc_id].payload[0]; in assert_dmc_loaded()
633 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { in assert_dmc_loaded()
634 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; in assert_dmc_loaded()
637 expected = dmc_mmiodata(display, dmc, dmc_id, i); in assert_dmc_loaded()
786 struct intel_dmc *dmc = display_to_dmc(display); in dmc_configure_event() local
790 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { in dmc_configure_event()
791 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; in dmc_configure_event()
792 u32 data = dmc->dmc_info[dmc_id].mmiodata[i]; in dmc_configure_event()
923 static void dmc_set_fw_offset(struct intel_dmc *dmc, in dmc_set_fw_offset() argument
929 struct intel_display *display = dmc->display; in dmc_set_fw_offset()
945 if (dmc->dmc_info[dmc_id].present) in dmc_set_fw_offset()
949 dmc->dmc_info[dmc_id].present = true; in dmc_set_fw_offset()
950 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; in dmc_set_fw_offset()
955 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, in dmc_mmio_addr_sanity_check() argument
959 struct intel_display *display = dmc->display; in dmc_mmio_addr_sanity_check()
988 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, in parse_dmc_fw_header() argument
992 struct intel_display *display = dmc->display; in parse_dmc_fw_header()
993 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; in parse_dmc_fw_header()
1057 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, in parse_dmc_fw_header()
1085 if (payload_size > dmc->max_fw_size) { in parse_dmc_fw_header()
1106 parse_dmc_fw_package(struct intel_dmc *dmc, in parse_dmc_fw_package() argument
1111 struct intel_display *display = dmc->display; in parse_dmc_fw_package()
1149 dmc_set_fw_offset(dmc, fw_info, num_entries, si, in parse_dmc_fw_package()
1161 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, in parse_dmc_fw_css() argument
1165 struct intel_display *display = dmc->display; in parse_dmc_fw_css()
1180 dmc->version = css_header->version; in parse_dmc_fw_css()
1185 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) in parse_dmc_fw() argument
1187 struct intel_display *display = dmc->display; in parse_dmc_fw()
1202 r = parse_dmc_fw_css(dmc, css_header, fw->size); in parse_dmc_fw()
1210 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); in parse_dmc_fw()
1217 if (!dmc->dmc_info[dmc_id].present) in parse_dmc_fw()
1220 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; in parse_dmc_fw()
1227 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); in parse_dmc_fw()
1240 drm_WARN_ON(display->drm, display->dmc.wakeref); in intel_dmc_runtime_pm_get()
1241 display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); in intel_dmc_runtime_pm_get()
1247 fetch_and_zero(&display->dmc.wakeref); in intel_dmc_runtime_pm_put()
1262 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); in dmc_load_work_fn() local
1263 struct intel_display *display = dmc->display; in dmc_load_work_fn()
1268 err = request_firmware(&fw, dmc->fw_path, display->drm->dev); in dmc_load_work_fn()
1274 dmc->fw_path, fallback_path); in dmc_load_work_fn()
1277 dmc->fw_path = fallback_path; in dmc_load_work_fn()
1284 dmc->fw_path, ERR_PTR(err)); in dmc_load_work_fn()
1290 err = parse_dmc_fw(dmc, fw); in dmc_load_work_fn()
1294 dmc->fw_path, ERR_PTR(err)); in dmc_load_work_fn()
1302 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), in dmc_load_work_fn()
1303 DMC_VERSION_MINOR(dmc->version)); in dmc_load_work_fn()
1318 struct intel_dmc *dmc; in intel_dmc_init() local
1333 dmc = kzalloc(sizeof(*dmc), GFP_KERNEL); in intel_dmc_init()
1334 if (!dmc) in intel_dmc_init()
1337 dmc->display = display; in intel_dmc_init()
1339 INIT_WORK(&dmc->work, dmc_load_work_fn); in intel_dmc_init()
1341 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); in intel_dmc_init()
1349 dmc->fw_path = dmc_firmware_param(display); in intel_dmc_init()
1351 if (!dmc->fw_path) { in intel_dmc_init()
1357 display->dmc.dmc = dmc; in intel_dmc_init()
1359 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); in intel_dmc_init()
1360 queue_work(display->wq.unordered, &dmc->work); in intel_dmc_init()
1365 kfree(dmc); in intel_dmc_init()
1378 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_suspend() local
1383 if (dmc) in intel_dmc_suspend()
1384 flush_work(&dmc->work); in intel_dmc_suspend()
1393 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_wait_fw_load() local
1398 if (dmc) in intel_dmc_wait_fw_load()
1399 flush_work(&dmc->work); in intel_dmc_wait_fw_load()
1431 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_fini() local
1438 drm_WARN_ON(display->drm, display->dmc.wakeref); in intel_dmc_fini()
1440 if (dmc) { in intel_dmc_fini()
1442 kfree(dmc->dmc_info[dmc_id].payload); in intel_dmc_fini()
1444 kfree(dmc); in intel_dmc_fini()
1445 display->dmc.dmc = NULL; in intel_dmc_fini()
1457 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_snapshot_capture() local
1467 snapshot->initialized = dmc; in intel_dmc_snapshot_capture()
1469 if (dmc) in intel_dmc_snapshot_capture()
1470 snapshot->version = dmc->version; in intel_dmc_snapshot_capture()
1491 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_update_dc6_allowed_count() local
1494 if (DISPLAY_VER(dmc->display) < 14) in intel_dmc_update_dc6_allowed_count()
1497 dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT); in intel_dmc_update_dc6_allowed_count()
1500 dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start; in intel_dmc_update_dc6_allowed_count()
1502 dmc->dc6_allowed.dc5_start = dc5_cur_count; in intel_dmc_update_dc6_allowed_count()
1508 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_get_dc6_allowed_count() local
1520 *count = dmc->dc6_allowed.count; in intel_dmc_get_dc6_allowed_count()
1529 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_debugfs_status_show() local
1539 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); in intel_dmc_debugfs_status_show()
1542 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); in intel_dmc_debugfs_status_show()
1556 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), in intel_dmc_debugfs_status_show()
1557 DMC_VERSION_MINOR(dmc->version)); in intel_dmc_debugfs_status_show()
1590 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); in intel_dmc_debugfs_status_show()
1676 struct intel_dmc *dmc = display_to_dmc(display); in intel_pipedmc_start_mmioaddr() local
1679 return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0; in intel_pipedmc_start_mmioaddr()