Lines Matching refs:dmc_id
299 u8 dmc_id; member
394 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) in is_valid_dmc_id() argument
396 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; in is_valid_dmc_id()
399 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) in has_dmc_id_fw() argument
403 return dmc && dmc->dmc_info[dmc_id].payload; in has_dmc_id_fw()
442 enum intel_dmc_id dmc_id) in disable_all_event_handlers() argument
450 if (!has_dmc_id_fw(display, dmc_id)) in disable_all_event_handlers()
455 DMC_EVT_CTL(display, dmc_id, handler), in disable_all_event_handlers()
456 DMC_EVT_HTP(display, dmc_id, handler)); in disable_all_event_handlers()
521 enum intel_dmc_id dmc_id, i915_reg_t reg) in is_dmc_evt_ctl_reg() argument
524 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); in is_dmc_evt_ctl_reg()
525 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); in is_dmc_evt_ctl_reg()
531 enum intel_dmc_id dmc_id, i915_reg_t reg) in is_dmc_evt_htp_reg() argument
534 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); in is_dmc_evt_htp_reg()
535 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); in is_dmc_evt_htp_reg()
541 enum intel_dmc_id dmc_id, in is_event_handler() argument
545 return is_dmc_evt_ctl_reg(display, dmc_id, reg) && in is_event_handler()
550 enum intel_dmc_id dmc_id, in disable_dmc_evt() argument
553 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) in disable_dmc_evt()
557 if (dmc_id != DMC_FW_MAIN) in disable_dmc_evt()
562 is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data)) in disable_dmc_evt()
567 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg, data)) in disable_dmc_evt()
575 enum intel_dmc_id dmc_id, int i) in dmc_mmiodata() argument
577 if (disable_dmc_evt(display, dmc_id, in dmc_mmiodata()
578 dmc->dmc_info[dmc_id].mmioaddr[i], in dmc_mmiodata()
579 dmc->dmc_info[dmc_id].mmiodata[i])) in dmc_mmiodata()
582 return dmc->dmc_info[dmc_id].mmiodata[i]; in dmc_mmiodata()
585 static void dmc_load_mmio(struct intel_display *display, enum intel_dmc_id dmc_id) in dmc_load_mmio() argument
590 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { in dmc_load_mmio()
591 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], in dmc_load_mmio()
592 dmc_mmiodata(display, dmc, dmc_id, i)); in dmc_load_mmio()
596 static void dmc_load_program(struct intel_display *display, enum intel_dmc_id dmc_id) in dmc_load_program() argument
601 disable_all_event_handlers(display, dmc_id); in dmc_load_program()
605 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { in dmc_load_program()
607 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), in dmc_load_program()
608 dmc->dmc_info[dmc_id].payload[i]); in dmc_load_program()
613 dmc_load_mmio(display, dmc_id); in dmc_load_program()
617 enum intel_dmc_id dmc_id) in assert_dmc_loaded() argument
623 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) in assert_dmc_loaded()
626 found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0)); in assert_dmc_loaded()
627 expected = dmc->dmc_info[dmc_id].payload[0]; in assert_dmc_loaded()
631 dmc_id, expected, found); in assert_dmc_loaded()
633 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { in assert_dmc_loaded()
634 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; in assert_dmc_loaded()
637 expected = dmc_mmiodata(display, dmc, dmc_id, i); in assert_dmc_loaded()
640 if (is_dmc_evt_ctl_reg(display, dmc_id, reg)) { in assert_dmc_loaded()
647 dmc_id, i, i915_mmio_reg_offset(reg), expected, found); in assert_dmc_loaded()
728 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); in intel_dmc_enable_pipe() local
730 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) in intel_dmc_enable_pipe()
739 dmc_load_program(display, dmc_id); in intel_dmc_enable_pipe()
741 dmc_load_mmio(display, dmc_id); in intel_dmc_enable_pipe()
743 assert_dmc_loaded(display, dmc_id); in intel_dmc_enable_pipe()
763 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); in intel_dmc_disable_pipe() local
765 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) in intel_dmc_disable_pipe()
782 enum intel_dmc_id dmc_id, in dmc_configure_event() argument
790 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { in dmc_configure_event()
791 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; in dmc_configure_event()
792 u32 data = dmc->dmc_info[dmc_id].mmiodata[i]; in dmc_configure_event()
794 if (!is_event_handler(display, dmc_id, event_id, reg, data)) in dmc_configure_event()
803 dmc_id, num_handlers, event_id); in dmc_configure_event()
836 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); in intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() local
838 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable); in intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank()
852 enum intel_dmc_id dmc_id; in intel_dmc_load_program() local
861 for_each_dmc_id(dmc_id) { in intel_dmc_load_program()
862 dmc_load_program(display, dmc_id); in intel_dmc_load_program()
863 assert_dmc_loaded(display, dmc_id); in intel_dmc_load_program()
889 enum intel_dmc_id dmc_id; in intel_dmc_disable_program() local
896 for_each_dmc_id(dmc_id) in intel_dmc_disable_program()
897 disable_all_event_handlers(display, dmc_id); in intel_dmc_disable_program()
930 enum intel_dmc_id dmc_id; in dmc_set_fw_offset() local
934 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; in dmc_set_fw_offset()
936 if (!is_valid_dmc_id(dmc_id)) { in dmc_set_fw_offset()
937 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); in dmc_set_fw_offset()
945 if (dmc->dmc_info[dmc_id].present) in dmc_set_fw_offset()
949 dmc->dmc_info[dmc_id].present = true; in dmc_set_fw_offset()
950 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; in dmc_set_fw_offset()
957 int header_ver, enum intel_dmc_id dmc_id) in dmc_mmio_addr_sanity_check() argument
966 } else if (dmc_id == DMC_FW_MAIN) { in dmc_mmio_addr_sanity_check()
973 start_range = TGL_PIPE_MMIO_START(dmc_id); in dmc_mmio_addr_sanity_check()
974 end_range = TGL_PIPE_MMIO_END(dmc_id); in dmc_mmio_addr_sanity_check()
990 size_t rem_size, enum intel_dmc_id dmc_id) in parse_dmc_fw_header() argument
993 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; in parse_dmc_fw_header()
1058 dmc_header->header_ver, dmc_id)) { in parse_dmc_fw_header()
1063 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); in parse_dmc_fw_header()
1070 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : in parse_dmc_fw_header()
1071 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", in parse_dmc_fw_header()
1072 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], in parse_dmc_fw_header()
1193 enum intel_dmc_id dmc_id; in parse_dmc_fw() local
1216 for_each_dmc_id(dmc_id) { in parse_dmc_fw()
1217 if (!dmc->dmc_info[dmc_id].present) in parse_dmc_fw()
1220 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; in parse_dmc_fw()
1227 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); in parse_dmc_fw()
1432 enum intel_dmc_id dmc_id; in intel_dmc_fini() local
1441 for_each_dmc_id(dmc_id) in intel_dmc_fini()
1442 kfree(dmc->dmc_info[dmc_id].payload); in intel_dmc_fini()
1659 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); in intel_pipedmc_enable_event() local
1661 dmc_configure_event(display, dmc_id, event, true); in intel_pipedmc_enable_event()
1668 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); in intel_pipedmc_disable_event() local
1670 dmc_configure_event(display, dmc_id, event, false); in intel_pipedmc_disable_event()
1677 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); in intel_pipedmc_start_mmioaddr() local
1679 return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0; in intel_pipedmc_start_mmioaddr()