Lines Matching refs:mode_clock
819 u32 intel_dp_mode_to_fec_clock(u32 mode_clock) in intel_dp_mode_to_fec_clock() argument
821 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR), in intel_dp_mode_to_fec_clock()
901 static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock, in bigjoiner_bw_max_bpp() argument
910 intel_dp_mode_to_fec_clock(mode_clock); in bigjoiner_bw_max_bpp()
945 u32 mode_clock, u32 mode_hdisplay, in get_max_compressed_bpp_with_joiner() argument
951 max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock, in get_max_compressed_bpp_with_joiner()
962 u32 mode_clock, u32 mode_hdisplay, in intel_dp_dsc_get_max_compressed_bpp() argument
987 (intel_dp_mode_to_fec_clock(mode_clock) * 8); in intel_dp_dsc_get_max_compressed_bpp()
1006 intel_dp_mode_to_fec_clock(mode_clock)); in intel_dp_dsc_get_max_compressed_bpp()
1008 joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock, in intel_dp_dsc_get_max_compressed_bpp()
1018 int mode_clock, int mode_hdisplay, in intel_dp_dsc_get_slice_count() argument
1025 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) in intel_dp_dsc_get_slice_count()
1026 min_slice_count = DIV_ROUND_UP(mode_clock, in intel_dp_dsc_get_slice_count()
1029 min_slice_count = DIV_ROUND_UP(mode_clock, in intel_dp_dsc_get_slice_count()
1036 if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100)) in intel_dp_dsc_get_slice_count()
1957 u32 lane_count, u32 mode_clock, in is_bw_sufficient_for_dsc_config() argument
1964 required_bw = dsc_bpp_x16 * (intel_dp_mode_to_fec_clock(mode_clock)); in is_bw_sufficient_for_dsc_config()