Lines Matching refs:pipe_bpp
850 static u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp) in intel_dp_dsc_nearest_valid_bpp() argument
864 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); in intel_dp_dsc_nearest_valid_bpp()
965 u32 pipe_bpp, in intel_dp_dsc_get_max_compressed_bpp() argument
1012 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bits_per_pixel, pipe_bpp); in intel_dp_dsc_get_max_compressed_bpp()
1470 int pipe_bpp; in intel_dp_mode_valid() local
1478 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); in intel_dp_mode_valid()
1499 pipe_bpp, 64); in intel_dp_mode_valid()
1711 bpc = crtc_state->pipe_bpp / 3; in intel_dp_max_bpp()
1801 pipe_config->pipe_bpp = bpp; in intel_dp_compute_link_config_wide()
2161 int pipe_bpp, in dsc_compute_compressed_bpp() argument
2182 output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); in dsc_compute_compressed_bpp()
2221 int pipe_bpp) in is_dsc_pipe_bpp_sufficient() argument
2223 return pipe_bpp >= limits->pipe.min_bpp && in is_dsc_pipe_bpp_sufficient()
2224 pipe_bpp <= limits->pipe.max_bpp; in is_dsc_pipe_bpp_sufficient()
2261 int forced_bpp, pipe_bpp; in intel_dp_dsc_compute_pipe_bpp() local
2270 pipe_config->pipe_bpp = forced_bpp; in intel_dp_dsc_compute_pipe_bpp()
2281 pipe_bpp = dsc_bpc[i] * 3; in intel_dp_dsc_compute_pipe_bpp()
2282 if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp) in intel_dp_dsc_compute_pipe_bpp()
2286 limits, pipe_bpp, timeslots); in intel_dp_dsc_compute_pipe_bpp()
2288 pipe_config->pipe_bpp = pipe_bpp; in intel_dp_dsc_compute_pipe_bpp()
2304 int pipe_bpp, forced_bpp; in intel_edp_dsc_compute_pipe_bpp() local
2311 pipe_bpp = forced_bpp; in intel_edp_dsc_compute_pipe_bpp()
2316 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc); in intel_edp_dsc_compute_pipe_bpp()
2317 if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) { in intel_edp_dsc_compute_pipe_bpp()
2331 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); in intel_edp_dsc_compute_pipe_bpp()
2336 pipe_config->pipe_bpp = pipe_bpp; in intel_edp_dsc_compute_pipe_bpp()
2446 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
2454 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
2564 limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24); in intel_dp_compute_config_limits()
2604 crtc_state->pipe_bpp; in intel_dp_config_required_rate()
2669 fxp_q4_from_int(pipe_config->pipe_bpp), in intel_dp_compute_link_config()
2670 fxp_q4_from_int(pipe_config->pipe_bpp), in intel_dp_compute_link_config()
2702 pipe_config->pipe_bpp, in intel_dp_compute_link_config()
2736 return crtc_state->pipe_bpp != 18 && in intel_dp_limited_color_range()
2833 vsc->bpc = crtc_state->pipe_bpp / 3; in intel_dp_compute_vsc_colorimetry()
3163 crtc_state->pipe_bpp)); in intel_dp_compute_min_hblank()
3255 pipe_config->pipe_bpp)); in intel_dp_compute_config()
4214 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp) in intel_edp_fixup_vbt_bpp() argument
4220 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) { in intel_edp_fixup_vbt_bpp()
4236 pipe_bpp, connector->panel.vbt.edp.bpp); in intel_edp_fixup_vbt_bpp()
4237 connector->panel.vbt.edp.bpp = pipe_bpp; in intel_edp_fixup_vbt_bpp()