Lines Matching refs:drm
271 drm_WARN(display->drm, 1, "PHY not found for PORT %c", in bxt_port_to_phy_channel()
305 if (drm_WARN_ON_ONCE(display->drm, !trans)) in bxt_dpio_phy_set_signal_levels()
338 drm_err(display->drm, in bxt_dpio_phy_set_signal_levels()
367 drm_dbg(display->drm, in bxt_dpio_phy_is_enabled()
374 drm_dbg(display->drm, in bxt_dpio_phy_is_enabled()
394 drm_err(display->drm, "timeout waiting for PHY%d GRC\n", phy); in bxt_phy_wait_grc_done()
410 drm_dbg(display->drm, "DDI PHY %d already enabled, " in _bxt_dpio_phy_init()
415 drm_dbg(display->drm, in _bxt_dpio_phy_init()
432 drm_err(display->drm, "timeout during PHY%d power on\n", in _bxt_dpio_phy_init()
530 drm_dbg(display->drm, "DDI PHY %d reg %pV [%08x] state mismatch: " in __phy_reg_verify_state()
727 vlv_dpio_get(display->drm); in chv_set_phy_signal_level()
730 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
734 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val); in chv_set_phy_signal_level()
737 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
741 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val); in chv_set_phy_signal_level()
744 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW9(ch)); in chv_set_phy_signal_level()
747 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW9(ch), val); in chv_set_phy_signal_level()
750 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW9(ch)); in chv_set_phy_signal_level()
753 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW9(ch), val); in chv_set_phy_signal_level()
758 val = vlv_dpio_read(display->drm, phy, CHV_TX_DW4(ch, i)); in chv_set_phy_signal_level()
761 vlv_dpio_write(display->drm, phy, CHV_TX_DW4(ch, i), val); in chv_set_phy_signal_level()
766 val = vlv_dpio_read(display->drm, phy, CHV_TX_DW2(ch, i)); in chv_set_phy_signal_level()
779 vlv_dpio_write(display->drm, phy, CHV_TX_DW2(ch, i), val); in chv_set_phy_signal_level()
789 val = vlv_dpio_read(display->drm, phy, CHV_TX_DW3(ch, i)); in chv_set_phy_signal_level()
794 vlv_dpio_write(display->drm, phy, CHV_TX_DW3(ch, i), val); in chv_set_phy_signal_level()
798 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
800 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val); in chv_set_phy_signal_level()
803 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
805 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val); in chv_set_phy_signal_level()
808 vlv_dpio_put(display->drm); in chv_set_phy_signal_level()
821 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW0(ch)); in __chv_data_lane_soft_reset()
826 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW0(ch), val); in __chv_data_lane_soft_reset()
829 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW0(ch)); in __chv_data_lane_soft_reset()
834 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW0(ch), val); in __chv_data_lane_soft_reset()
837 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW1(ch)); in __chv_data_lane_soft_reset()
843 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW1(ch), val); in __chv_data_lane_soft_reset()
846 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW1(ch)); in __chv_data_lane_soft_reset()
852 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW1(ch), val); in __chv_data_lane_soft_reset()
862 vlv_dpio_get(display->drm); in chv_data_lane_soft_reset()
864 vlv_dpio_put(display->drm); in chv_data_lane_soft_reset()
890 vlv_dpio_get(display->drm); in chv_phy_pre_pll_enable()
897 val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0); in chv_phy_pre_pll_enable()
903 vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val); in chv_phy_pre_pll_enable()
905 val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1); in chv_phy_pre_pll_enable()
911 vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val); in chv_phy_pre_pll_enable()
915 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW8(ch)); in chv_phy_pre_pll_enable()
921 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW8(ch), val); in chv_phy_pre_pll_enable()
924 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW8(ch)); in chv_phy_pre_pll_enable()
930 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW8(ch), val); in chv_phy_pre_pll_enable()
938 val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW19(ch)); in chv_phy_pre_pll_enable()
943 vlv_dpio_write(display->drm, phy, CHV_CMN_DW19(ch), val); in chv_phy_pre_pll_enable()
945 vlv_dpio_put(display->drm); in chv_phy_pre_pll_enable()
959 vlv_dpio_get(display->drm); in chv_phy_pre_encoder_enable()
962 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch)); in chv_phy_pre_encoder_enable()
964 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val); in chv_phy_pre_encoder_enable()
967 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch)); in chv_phy_pre_encoder_enable()
969 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val); in chv_phy_pre_encoder_enable()
979 vlv_dpio_write(display->drm, phy, CHV_TX_DW14(ch, i), data); in chv_phy_pre_encoder_enable()
994 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch)); in chv_phy_pre_encoder_enable()
996 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val); in chv_phy_pre_encoder_enable()
999 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch)); in chv_phy_pre_encoder_enable()
1001 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val); in chv_phy_pre_encoder_enable()
1004 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW12(ch), in chv_phy_pre_encoder_enable()
1012 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW12(ch), in chv_phy_pre_encoder_enable()
1023 vlv_dpio_put(display->drm); in chv_phy_pre_encoder_enable()
1045 vlv_dpio_get(display->drm); in chv_phy_post_pll_disable()
1049 val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0); in chv_phy_post_pll_disable()
1051 vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val); in chv_phy_post_pll_disable()
1053 val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1); in chv_phy_post_pll_disable()
1055 vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val); in chv_phy_post_pll_disable()
1058 vlv_dpio_put(display->drm); in chv_phy_post_pll_disable()
1082 vlv_dpio_get(display->drm); in vlv_set_phy_signal_level()
1084 vlv_dpio_write(display->drm, phy, VLV_TX_DW5_GRP(ch), 0x00000000); in vlv_set_phy_signal_level()
1085 vlv_dpio_write(display->drm, phy, VLV_TX_DW4_GRP(ch), demph_reg_value); in vlv_set_phy_signal_level()
1086 vlv_dpio_write(display->drm, phy, VLV_TX_DW2_GRP(ch), in vlv_set_phy_signal_level()
1088 vlv_dpio_write(display->drm, phy, VLV_TX_DW3_GRP(ch), 0x0C782040); in vlv_set_phy_signal_level()
1091 vlv_dpio_write(display->drm, phy, VLV_TX_DW4(ch, 3), tx3_demph); in vlv_set_phy_signal_level()
1093 vlv_dpio_write(display->drm, phy, VLV_PCS_DW11_GRP(ch), 0x00030000); in vlv_set_phy_signal_level()
1094 vlv_dpio_write(display->drm, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value); in vlv_set_phy_signal_level()
1095 vlv_dpio_write(display->drm, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN); in vlv_set_phy_signal_level()
1097 vlv_dpio_put(display->drm); in vlv_set_phy_signal_level()
1109 vlv_dpio_get(display->drm); in vlv_phy_pre_pll_enable()
1111 vlv_dpio_write(display->drm, phy, VLV_PCS_DW0_GRP(ch), in vlv_phy_pre_pll_enable()
1114 vlv_dpio_write(display->drm, phy, VLV_PCS_DW1_GRP(ch), in vlv_phy_pre_pll_enable()
1121 vlv_dpio_write(display->drm, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00); in vlv_phy_pre_pll_enable()
1122 vlv_dpio_write(display->drm, phy, VLV_TX_DW11_GRP(ch), 0x00001500); in vlv_phy_pre_pll_enable()
1123 vlv_dpio_write(display->drm, phy, VLV_TX_DW14_GRP(ch), 0x40400000); in vlv_phy_pre_pll_enable()
1125 vlv_dpio_put(display->drm); in vlv_phy_pre_pll_enable()
1140 vlv_dpio_get(display->drm); in vlv_phy_pre_encoder_enable()
1147 vlv_dpio_write(display->drm, phy, VLV_PCS_DW8_GRP(ch), val); in vlv_phy_pre_encoder_enable()
1150 vlv_dpio_write(display->drm, phy, VLV_PCS_DW14_GRP(ch), 0x00760018); in vlv_phy_pre_encoder_enable()
1151 vlv_dpio_write(display->drm, phy, VLV_PCS_DW23_GRP(ch), 0x00400888); in vlv_phy_pre_encoder_enable()
1153 vlv_dpio_put(display->drm); in vlv_phy_pre_encoder_enable()
1164 vlv_dpio_get(display->drm); in vlv_phy_reset_lanes()
1165 vlv_dpio_write(display->drm, phy, VLV_PCS_DW0_GRP(ch), 0x00000000); in vlv_phy_reset_lanes()
1166 vlv_dpio_write(display->drm, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060); in vlv_phy_reset_lanes()
1167 vlv_dpio_put(display->drm); in vlv_phy_reset_lanes()
1197 drm_WARN(display->drm, 1, in vlv_wait_port_ready()