Lines Matching refs:clock
318 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params() argument
320 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
321 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
323 clock->vco = clock->n == 0 ? 0 : in pnv_calc_dpll_params()
324 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
325 clock->dot = clock->p == 0 ? 0 : in pnv_calc_dpll_params()
326 DIV_ROUND_CLOSEST(clock->vco, clock->p); in pnv_calc_dpll_params()
328 return clock->dot; in pnv_calc_dpll_params()
336 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params() argument
338 clock->m = i9xx_dpll_compute_m(clock); in i9xx_calc_dpll_params()
339 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
341 clock->vco = clock->n + 2 == 0 ? 0 : in i9xx_calc_dpll_params()
342 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); in i9xx_calc_dpll_params()
343 clock->dot = clock->p == 0 ? 0 : in i9xx_calc_dpll_params()
344 DIV_ROUND_CLOSEST(clock->vco, clock->p); in i9xx_calc_dpll_params()
346 return clock->dot; in i9xx_calc_dpll_params()
349 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params() argument
351 clock->m = clock->m1 * clock->m2; in vlv_calc_dpll_params()
352 clock->p = clock->p1 * clock->p2 * 5; in vlv_calc_dpll_params()
354 clock->vco = clock->n == 0 ? 0 : in vlv_calc_dpll_params()
355 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in vlv_calc_dpll_params()
356 clock->dot = clock->p == 0 ? 0 : in vlv_calc_dpll_params()
357 DIV_ROUND_CLOSEST(clock->vco, clock->p); in vlv_calc_dpll_params()
359 return clock->dot; in vlv_calc_dpll_params()
362 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params() argument
364 clock->m = clock->m1 * clock->m2; in chv_calc_dpll_params()
365 clock->p = clock->p1 * clock->p2 * 5; in chv_calc_dpll_params()
367 clock->vco = clock->n == 0 ? 0 : in chv_calc_dpll_params()
368 DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22); in chv_calc_dpll_params()
369 clock->dot = clock->p == 0 ? 0 : in chv_calc_dpll_params()
370 DIV_ROUND_CLOSEST(clock->vco, clock->p); in chv_calc_dpll_params()
372 return clock->dot; in chv_calc_dpll_params()
430 struct dpll clock; in i9xx_crtc_clock_get() local
439 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; in i9xx_crtc_clock_get()
441 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; in i9xx_crtc_clock_get()
442 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; in i9xx_crtc_clock_get()
444 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; in i9xx_crtc_clock_get()
445 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; in i9xx_crtc_clock_get()
450 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> in i9xx_crtc_clock_get()
453 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> in i9xx_crtc_clock_get()
458 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? in i9xx_crtc_clock_get()
462 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? in i9xx_crtc_clock_get()
473 port_clock = pnv_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
475 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
484 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()
488 clock.p2 = 7; in i9xx_crtc_clock_get()
490 clock.p2 = 14; in i9xx_crtc_clock_get()
493 clock.p1 = 2; in i9xx_crtc_clock_get()
495 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> in i9xx_crtc_clock_get()
499 clock.p2 = 4; in i9xx_crtc_clock_get()
501 clock.p2 = 2; in i9xx_crtc_clock_get()
504 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
523 struct dpll clock; in vlv_crtc_clock_get() local
534 clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp); in vlv_crtc_clock_get()
535 clock.m2 = REG_FIELD_GET(DPIO_M2_DIV_MASK, tmp); in vlv_crtc_clock_get()
536 clock.n = REG_FIELD_GET(DPIO_N_DIV_MASK, tmp); in vlv_crtc_clock_get()
537 clock.p1 = REG_FIELD_GET(DPIO_P1_DIV_MASK, tmp); in vlv_crtc_clock_get()
538 clock.p2 = REG_FIELD_GET(DPIO_P2_DIV_MASK, tmp); in vlv_crtc_clock_get()
540 crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
550 struct dpll clock; in chv_crtc_clock_get() local
566 clock.m1 = REG_FIELD_GET(DPIO_CHV_M1_DIV_MASK, pll_dw1) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; in chv_crtc_clock_get()
567 clock.m2 = REG_FIELD_GET(DPIO_CHV_M2_DIV_MASK, pll_dw0) << 22; in chv_crtc_clock_get()
569 clock.m2 |= REG_FIELD_GET(DPIO_CHV_M2_FRAC_DIV_MASK, pll_dw2); in chv_crtc_clock_get()
570 clock.n = REG_FIELD_GET(DPIO_CHV_N_DIV_MASK, pll_dw1); in chv_crtc_clock_get()
571 clock.p1 = REG_FIELD_GET(DPIO_CHV_P1_DIV_MASK, cmn_dw13); in chv_crtc_clock_get()
572 clock.p2 = REG_FIELD_GET(DPIO_CHV_P2_DIV_MASK, cmn_dw13); in chv_crtc_clock_get()
574 crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock); in chv_crtc_clock_get()
583 const struct dpll *clock) in intel_pll_is_valid() argument
585 if (clock->n < limit->n.min || limit->n.max < clock->n) in intel_pll_is_valid()
587 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in intel_pll_is_valid()
589 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in intel_pll_is_valid()
591 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in intel_pll_is_valid()
597 if (clock->m1 <= clock->m2) in intel_pll_is_valid()
602 if (clock->p < limit->p.min || limit->p.max < clock->p) in intel_pll_is_valid()
604 if (clock->m < limit->m.min || limit->m.max < clock->m) in intel_pll_is_valid()
608 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in intel_pll_is_valid()
613 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in intel_pll_is_valid()
661 struct dpll clock; in i9xx_find_best_dpll() local
666 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); in i9xx_find_best_dpll()
668 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in i9xx_find_best_dpll()
669 clock.m1++) { in i9xx_find_best_dpll()
670 for (clock.m2 = limit->m2.min; in i9xx_find_best_dpll()
671 clock.m2 <= limit->m2.max; clock.m2++) { in i9xx_find_best_dpll()
672 if (clock.m2 >= clock.m1) in i9xx_find_best_dpll()
674 for (clock.n = limit->n.min; in i9xx_find_best_dpll()
675 clock.n <= limit->n.max; clock.n++) { in i9xx_find_best_dpll()
676 for (clock.p1 = limit->p1.min; in i9xx_find_best_dpll()
677 clock.p1 <= limit->p1.max; clock.p1++) { in i9xx_find_best_dpll()
680 i9xx_calc_dpll_params(refclk, &clock); in i9xx_find_best_dpll()
683 &clock)) in i9xx_find_best_dpll()
686 clock.p != match_clock->p) in i9xx_find_best_dpll()
689 this_err = abs(clock.dot - target); in i9xx_find_best_dpll()
691 *best_clock = clock; in i9xx_find_best_dpll()
719 struct dpll clock; in pnv_find_best_dpll() local
724 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); in pnv_find_best_dpll()
726 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in pnv_find_best_dpll()
727 clock.m1++) { in pnv_find_best_dpll()
728 for (clock.m2 = limit->m2.min; in pnv_find_best_dpll()
729 clock.m2 <= limit->m2.max; clock.m2++) { in pnv_find_best_dpll()
730 for (clock.n = limit->n.min; in pnv_find_best_dpll()
731 clock.n <= limit->n.max; clock.n++) { in pnv_find_best_dpll()
732 for (clock.p1 = limit->p1.min; in pnv_find_best_dpll()
733 clock.p1 <= limit->p1.max; clock.p1++) { in pnv_find_best_dpll()
736 pnv_calc_dpll_params(refclk, &clock); in pnv_find_best_dpll()
739 &clock)) in pnv_find_best_dpll()
742 clock.p != match_clock->p) in pnv_find_best_dpll()
745 this_err = abs(clock.dot - target); in pnv_find_best_dpll()
747 *best_clock = clock; in pnv_find_best_dpll()
775 struct dpll clock; in g4x_find_best_dpll() local
783 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); in g4x_find_best_dpll()
787 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in g4x_find_best_dpll()
789 for (clock.m1 = limit->m1.max; in g4x_find_best_dpll()
790 clock.m1 >= limit->m1.min; clock.m1--) { in g4x_find_best_dpll()
791 for (clock.m2 = limit->m2.max; in g4x_find_best_dpll()
792 clock.m2 >= limit->m2.min; clock.m2--) { in g4x_find_best_dpll()
793 for (clock.p1 = limit->p1.max; in g4x_find_best_dpll()
794 clock.p1 >= limit->p1.min; clock.p1--) { in g4x_find_best_dpll()
797 i9xx_calc_dpll_params(refclk, &clock); in g4x_find_best_dpll()
800 &clock)) in g4x_find_best_dpll()
803 this_err = abs(clock.dot - target); in g4x_find_best_dpll()
805 *best_clock = clock; in g4x_find_best_dpll()
807 max_n = clock.n; in g4x_find_best_dpll()
869 struct dpll clock; in vlv_find_best_dpll() local
878 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in vlv_find_best_dpll()
879 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in vlv_find_best_dpll()
880 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; in vlv_find_best_dpll()
881 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in vlv_find_best_dpll()
882 clock.p = clock.p1 * clock.p2 * 5; in vlv_find_best_dpll()
884 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { in vlv_find_best_dpll()
887 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, in vlv_find_best_dpll()
888 refclk * clock.m1); in vlv_find_best_dpll()
890 vlv_calc_dpll_params(refclk, &clock); in vlv_find_best_dpll()
894 &clock)) in vlv_find_best_dpll()
898 &clock, in vlv_find_best_dpll()
903 *best_clock = clock; in vlv_find_best_dpll()
927 struct dpll clock; in chv_find_best_dpll() local
939 clock.n = 1; in chv_find_best_dpll()
940 clock.m1 = 2; in chv_find_best_dpll()
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in chv_find_best_dpll()
943 for (clock.p2 = limit->p2.p2_fast; in chv_find_best_dpll()
944 clock.p2 >= limit->p2.p2_slow; in chv_find_best_dpll()
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in chv_find_best_dpll()
948 clock.p = clock.p1 * clock.p2 * 5; in chv_find_best_dpll()
950 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22, in chv_find_best_dpll()
951 refclk * clock.m1); in chv_find_best_dpll()
953 if (m2 > INT_MAX/clock.m1) in chv_find_best_dpll()
956 clock.m2 = m2; in chv_find_best_dpll()
958 chv_calc_dpll_params(refclk, &clock); in chv_find_best_dpll()
960 if (!intel_pll_is_valid(display, limit, &clock)) in chv_find_best_dpll()
963 if (!vlv_PLL_is_optimal(display, target, &clock, best_clock, in chv_find_best_dpll()
967 *best_clock = clock; in chv_find_best_dpll()
1003 const struct dpll *clock, in i9xx_dpll() argument
1031 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1034 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_dpll()
1035 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_dpll()
1037 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1038 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_dpll()
1041 switch (clock->p2) { in i9xx_dpll()
1055 WARN_ON(reduced_clock->p2 != clock->p2); in i9xx_dpll()
1072 const struct dpll *clock, in i9xx_compute_dpll() argument
1079 hw_state->fp0 = pnv_dpll_compute_fp(clock); in i9xx_compute_dpll()
1082 hw_state->fp0 = i9xx_dpll_compute_fp(clock); in i9xx_compute_dpll()
1086 hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock); in i9xx_compute_dpll()
1093 const struct dpll *clock, in i8xx_dpll() argument
1102 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1104 if (clock->p1 == 2) in i8xx_dpll()
1107 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1108 if (clock->p2 == 4) in i8xx_dpll()
1111 WARN_ON(reduced_clock->p1 != clock->p1); in i8xx_dpll()
1112 WARN_ON(reduced_clock->p2 != clock->p2); in i8xx_dpll()
1140 const struct dpll *clock, in i8xx_compute_dpll() argument
1145 hw_state->fp0 = i9xx_dpll_compute_fp(clock); in i8xx_compute_dpll()
1148 hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock); in i8xx_compute_dpll()
1255 static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor) in ilk_dpll_compute_fp() argument
1259 fp = i9xx_dpll_compute_fp(clock); in ilk_dpll_compute_fp()
1260 if (ilk_needs_fb_cb_tune(clock, factor)) in ilk_dpll_compute_fp()
1267 const struct dpll *clock, in ilk_dpll() argument
1309 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_dpll()
1313 switch (clock->p2) { in ilk_dpll()
1327 WARN_ON(reduced_clock->p2 != clock->p2); in ilk_dpll()
1339 const struct dpll *clock, in ilk_compute_dpll() argument
1345 hw_state->fp0 = ilk_dpll_compute_fp(clock, factor); in ilk_compute_dpll()
1348 hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock); in ilk_compute_dpll()
1905 const struct dpll *clock = &crtc_state->dpll; in vlv_prepare_pll() local
1931 tmp = DPIO_M1_DIV(clock->m1) | in vlv_prepare_pll()
1932 DPIO_M2_DIV(clock->m2) | in vlv_prepare_pll()
1933 DPIO_P1_DIV(clock->p1) | in vlv_prepare_pll()
1934 DPIO_P2_DIV(clock->p2) | in vlv_prepare_pll()
1935 DPIO_N_DIV(clock->n) | in vlv_prepare_pll()
2026 const struct dpll *clock = &crtc_state->dpll; in chv_prepare_pll() local
2032 m2_frac = clock->m2 & 0x3fffff; in chv_prepare_pll()
2039 DPIO_CHV_P1_DIV(clock->p1) | in chv_prepare_pll()
2040 DPIO_CHV_P2_DIV(clock->p2) | in chv_prepare_pll()
2045 DPIO_CHV_M2_DIV(clock->m2 >> 22)); in chv_prepare_pll()
2074 if (clock->vco == 5400000) { in chv_prepare_pll()
2079 } else if (clock->vco <= 6200000) { in chv_prepare_pll()
2084 } else if (clock->vco <= 6480000) { in chv_prepare_pll()