Lines Matching refs:dot
38 } dot, vco, n, m, m1, m2, p, p1; member
46 .dot = { .min = 25000, .max = 350000 },
59 .dot = { .min = 25000, .max = 350000 },
72 .dot = { .min = 25000, .max = 350000 },
85 .dot = { .min = 20000, .max = 400000 },
98 .dot = { .min = 20000, .max = 400000 },
112 .dot = { .min = 25000, .max = 270000 },
127 .dot = { .min = 22000, .max = 400000 },
140 .dot = { .min = 20000, .max = 115000 },
154 .dot = { .min = 80000, .max = 224000 },
168 .dot = { .min = 20000, .max = 400000},
183 .dot = { .min = 20000, .max = 400000 },
201 .dot = { .min = 25000, .max = 350000 },
214 .dot = { .min = 25000, .max = 350000 },
227 .dot = { .min = 25000, .max = 350000 },
241 .dot = { .min = 25000, .max = 350000 },
254 .dot = { .min = 25000, .max = 350000 },
273 .dot = { .min = 25000, .max = 270000 },
289 .dot = { .min = 25000, .max = 540000 },
299 .dot = { .min = 25000, .max = 594000 },
325 clock->dot = clock->p == 0 ? 0 : in pnv_calc_dpll_params()
328 return clock->dot; in pnv_calc_dpll_params()
343 clock->dot = clock->p == 0 ? 0 : in i9xx_calc_dpll_params()
346 return clock->dot; in i9xx_calc_dpll_params()
356 clock->dot = clock->p == 0 ? 0 : in vlv_calc_dpll_params()
359 return clock->dot; in vlv_calc_dpll_params()
369 clock->dot = clock->p == 0 ? 0 : in chv_calc_dpll_params()
372 return clock->dot; in chv_calc_dpll_params()
613 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in intel_pll_is_valid()
689 this_err = abs(clock.dot - target); in i9xx_find_best_dpll()
745 this_err = abs(clock.dot - target); in pnv_find_best_dpll()
803 this_err = abs(clock.dot - target); in g4x_find_best_dpll()
841 abs(target_freq - calculated_clock->dot), in vlv_PLL_is_optimal()
1402 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1494 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1521 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1568 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1608 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1646 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
1688 crtc_state->port_clock = crtc_state->dpll.dot; in i8xx_crtc_compute_clock()