Lines Matching refs:p2
43 } p2; member
54 .p2 = { .dot_limit = 165000,
67 .p2 = { .dot_limit = 165000,
80 .p2 = { .dot_limit = 165000,
93 .p2 = { .dot_limit = 200000,
106 .p2 = { .dot_limit = 112000,
120 .p2 = { .dot_limit = 270000,
135 .p2 = { .dot_limit = 165000,
148 .p2 = { .dot_limit = 0,
162 .p2 = { .dot_limit = 0,
178 .p2 = { .dot_limit = 200000,
191 .p2 = { .dot_limit = 112000,
209 .p2 = { .dot_limit = 225000,
222 .p2 = { .dot_limit = 225000,
235 .p2 = { .dot_limit = 225000,
249 .p2 = { .dot_limit = 225000,
262 .p2 = { .dot_limit = 225000,
279 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
295 .p2 = { .p2_slow = 1, .p2_fast = 14 },
306 .p2 = { .p2_slow = 1, .p2_fast = 20 },
321 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
339 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
352 clock->p = clock->p1 * clock->p2 * 5; in vlv_calc_dpll_params()
365 clock->p = clock->p1 * clock->p2 * 5; in chv_calc_dpll_params()
458 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? in i9xx_crtc_clock_get()
462 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? in i9xx_crtc_clock_get()
488 clock.p2 = 7; in i9xx_crtc_clock_get()
490 clock.p2 = 14; in i9xx_crtc_clock_get()
499 clock.p2 = 4; in i9xx_crtc_clock_get()
501 clock.p2 = 2; in i9xx_crtc_clock_get()
538 clock.p2 = REG_FIELD_GET(DPIO_P2_DIV_MASK, tmp); in vlv_crtc_clock_get()
572 clock.p2 = REG_FIELD_GET(DPIO_CHV_P2_DIV_MASK, cmn_dw13); in chv_crtc_clock_get()
633 return limit->p2.p2_fast; in i9xx_select_p2_div()
635 return limit->p2.p2_slow; in i9xx_select_p2_div()
637 if (target < limit->p2.dot_limit) in i9xx_select_p2_div()
638 return limit->p2.p2_slow; in i9xx_select_p2_div()
640 return limit->p2.p2_fast; in i9xx_select_p2_div()
666 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); in i9xx_find_best_dpll()
724 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); in pnv_find_best_dpll()
783 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); in g4x_find_best_dpll()
880 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; in vlv_find_best_dpll()
881 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in vlv_find_best_dpll()
882 clock.p = clock.p1 * clock.p2 * 5; in vlv_find_best_dpll()
943 for (clock.p2 = limit->p2.p2_fast; in chv_find_best_dpll()
944 clock.p2 >= limit->p2.p2_slow; in chv_find_best_dpll()
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in chv_find_best_dpll()
948 clock.p = clock.p1 * clock.p2 * 5; in chv_find_best_dpll()
1041 switch (clock->p2) { in i9xx_dpll()
1055 WARN_ON(reduced_clock->p2 != clock->p2); in i9xx_dpll()
1108 if (clock->p2 == 4) in i8xx_dpll()
1112 WARN_ON(reduced_clock->p2 != clock->p2); in i8xx_dpll()
1313 switch (clock->p2) { in ilk_dpll()
1327 WARN_ON(reduced_clock->p2 != clock->p2); in ilk_dpll()
1934 DPIO_P2_DIV(clock->p2) | in vlv_prepare_pll()
2040 DPIO_CHV_P2_DIV(clock->p2) | in chv_prepare_pll()