Lines Matching refs:display
60 static bool ivb_can_enable_err_int(struct intel_display *display) in ivb_can_enable_err_int() argument
65 lockdep_assert_held(&display->irq.lock); in ivb_can_enable_err_int()
67 for_each_pipe(display, pipe) { in ivb_can_enable_err_int()
68 crtc = intel_crtc_for_pipe(display, pipe); in ivb_can_enable_err_int()
77 static bool cpt_can_enable_serr_int(struct intel_display *display) in cpt_can_enable_serr_int() argument
82 lockdep_assert_held(&display->irq.lock); in cpt_can_enable_serr_int()
84 for_each_pipe(display, pipe) { in cpt_can_enable_serr_int()
85 crtc = intel_crtc_for_pipe(display, pipe); in cpt_can_enable_serr_int()
96 struct intel_display *display = to_intel_display(crtc); in i9xx_check_fifo_underruns() local
97 i915_reg_t reg = PIPESTAT(display, crtc->pipe); in i9xx_check_fifo_underruns()
100 lockdep_assert_held(&display->irq.lock); in i9xx_check_fifo_underruns()
102 if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
105 enable_mask = i915_pipestat_enable_mask(display, crtc->pipe); in i9xx_check_fifo_underruns()
106 intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_check_fifo_underruns()
107 intel_de_posting_read(display, reg); in i9xx_check_fifo_underruns()
109 trace_intel_cpu_fifo_underrun(display, crtc->pipe); in i9xx_check_fifo_underruns()
110 drm_err(display->drm, "pipe %c underrun\n", pipe_name(crtc->pipe)); in i9xx_check_fifo_underruns()
113 static void i9xx_set_fifo_underrun_reporting(struct intel_display *display, in i9xx_set_fifo_underrun_reporting() argument
117 i915_reg_t reg = PIPESTAT(display, pipe); in i9xx_set_fifo_underrun_reporting()
119 lockdep_assert_held(&display->irq.lock); in i9xx_set_fifo_underrun_reporting()
122 u32 enable_mask = i915_pipestat_enable_mask(display, pipe); in i9xx_set_fifo_underrun_reporting()
124 intel_de_write(display, reg, in i9xx_set_fifo_underrun_reporting()
126 intel_de_posting_read(display, reg); in i9xx_set_fifo_underrun_reporting()
128 if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
129 drm_err(display->drm, "pipe %c underrun\n", in i9xx_set_fifo_underrun_reporting()
134 static void ilk_set_fifo_underrun_reporting(struct intel_display *display, in ilk_set_fifo_underrun_reporting() argument
141 ilk_enable_display_irq(display, bit); in ilk_set_fifo_underrun_reporting()
143 ilk_disable_display_irq(display, bit); in ilk_set_fifo_underrun_reporting()
148 struct intel_display *display = to_intel_display(crtc); in ivb_check_fifo_underruns() local
150 u32 err_int = intel_de_read(display, GEN7_ERR_INT); in ivb_check_fifo_underruns()
152 lockdep_assert_held(&display->irq.lock); in ivb_check_fifo_underruns()
157 intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivb_check_fifo_underruns()
158 intel_de_posting_read(display, GEN7_ERR_INT); in ivb_check_fifo_underruns()
160 trace_intel_cpu_fifo_underrun(display, pipe); in ivb_check_fifo_underruns()
161 drm_err(display->drm, "fifo underrun on pipe %c\n", pipe_name(pipe)); in ivb_check_fifo_underruns()
164 static void ivb_set_fifo_underrun_reporting(struct intel_display *display, in ivb_set_fifo_underrun_reporting() argument
169 intel_de_write(display, GEN7_ERR_INT, in ivb_set_fifo_underrun_reporting()
172 if (!ivb_can_enable_err_int(display)) in ivb_set_fifo_underrun_reporting()
175 ilk_enable_display_irq(display, DE_ERR_INT_IVB); in ivb_set_fifo_underrun_reporting()
177 ilk_disable_display_irq(display, DE_ERR_INT_IVB); in ivb_set_fifo_underrun_reporting()
180 intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivb_set_fifo_underrun_reporting()
181 drm_err(display->drm, in ivb_set_fifo_underrun_reporting()
188 static void bdw_set_fifo_underrun_reporting(struct intel_display *display, in bdw_set_fifo_underrun_reporting() argument
192 bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN); in bdw_set_fifo_underrun_reporting()
194 bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN); in bdw_set_fifo_underrun_reporting()
197 static void ibx_set_fifo_underrun_reporting(struct intel_display *display, in ibx_set_fifo_underrun_reporting() argument
205 ibx_enable_display_interrupt(display, bit); in ibx_set_fifo_underrun_reporting()
207 ibx_disable_display_interrupt(display, bit); in ibx_set_fifo_underrun_reporting()
212 struct intel_display *display = to_intel_display(crtc); in cpt_check_pch_fifo_underruns() local
214 u32 serr_int = intel_de_read(display, SERR_INT); in cpt_check_pch_fifo_underruns()
216 lockdep_assert_held(&display->irq.lock); in cpt_check_pch_fifo_underruns()
221 intel_de_write(display, SERR_INT, in cpt_check_pch_fifo_underruns()
223 intel_de_posting_read(display, SERR_INT); in cpt_check_pch_fifo_underruns()
225 trace_intel_pch_fifo_underrun(display, pch_transcoder); in cpt_check_pch_fifo_underruns()
226 drm_err(display->drm, "pch fifo underrun on pch transcoder %c\n", in cpt_check_pch_fifo_underruns()
230 static void cpt_set_fifo_underrun_reporting(struct intel_display *display, in cpt_set_fifo_underrun_reporting() argument
235 intel_de_write(display, SERR_INT, in cpt_set_fifo_underrun_reporting()
238 if (!cpt_can_enable_serr_int(display)) in cpt_set_fifo_underrun_reporting()
241 ibx_enable_display_interrupt(display, SDE_ERROR_CPT); in cpt_set_fifo_underrun_reporting()
243 ibx_disable_display_interrupt(display, SDE_ERROR_CPT); in cpt_set_fifo_underrun_reporting()
245 if (old && intel_de_read(display, SERR_INT) & in cpt_set_fifo_underrun_reporting()
247 drm_err(display->drm, in cpt_set_fifo_underrun_reporting()
254 static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, in __intel_set_cpu_fifo_underrun_reporting() argument
257 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in __intel_set_cpu_fifo_underrun_reporting()
260 lockdep_assert_held(&display->irq.lock); in __intel_set_cpu_fifo_underrun_reporting()
265 if (HAS_GMCH(display)) in __intel_set_cpu_fifo_underrun_reporting()
266 i9xx_set_fifo_underrun_reporting(display, pipe, enable, old); in __intel_set_cpu_fifo_underrun_reporting()
267 else if (display->platform.ironlake || display->platform.sandybridge) in __intel_set_cpu_fifo_underrun_reporting()
268 ilk_set_fifo_underrun_reporting(display, pipe, enable); in __intel_set_cpu_fifo_underrun_reporting()
269 else if (DISPLAY_VER(display) == 7) in __intel_set_cpu_fifo_underrun_reporting()
270 ivb_set_fifo_underrun_reporting(display, pipe, enable, old); in __intel_set_cpu_fifo_underrun_reporting()
271 else if (DISPLAY_VER(display) >= 8) in __intel_set_cpu_fifo_underrun_reporting()
272 bdw_set_fifo_underrun_reporting(display, pipe, enable); in __intel_set_cpu_fifo_underrun_reporting()
293 bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, in intel_set_cpu_fifo_underrun_reporting() argument
299 spin_lock_irqsave(&display->irq.lock, flags); in intel_set_cpu_fifo_underrun_reporting()
300 ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable); in intel_set_cpu_fifo_underrun_reporting()
301 spin_unlock_irqrestore(&display->irq.lock, flags); in intel_set_cpu_fifo_underrun_reporting()
320 bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display, in intel_set_pch_fifo_underrun_reporting() argument
324 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pch_transcoder); in intel_set_pch_fifo_underrun_reporting()
337 spin_lock_irqsave(&display->irq.lock, flags); in intel_set_pch_fifo_underrun_reporting()
342 if (HAS_PCH_IBX(display)) in intel_set_pch_fifo_underrun_reporting()
343 ibx_set_fifo_underrun_reporting(display, in intel_set_pch_fifo_underrun_reporting()
347 cpt_set_fifo_underrun_reporting(display, in intel_set_pch_fifo_underrun_reporting()
351 spin_unlock_irqrestore(&display->irq.lock, flags); in intel_set_pch_fifo_underrun_reporting()
364 void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display, in intel_cpu_fifo_underrun_irq_handler() argument
367 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in intel_cpu_fifo_underrun_irq_handler()
374 if (HAS_GMCH(display) && in intel_cpu_fifo_underrun_irq_handler()
378 if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) { in intel_cpu_fifo_underrun_irq_handler()
379 trace_intel_cpu_fifo_underrun(display, pipe); in intel_cpu_fifo_underrun_irq_handler()
381 drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe)); in intel_cpu_fifo_underrun_irq_handler()
384 intel_fbc_handle_fifo_underrun_irq(display); in intel_cpu_fifo_underrun_irq_handler()
396 void intel_pch_fifo_underrun_irq_handler(struct intel_display *display, in intel_pch_fifo_underrun_irq_handler() argument
399 if (intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, in intel_pch_fifo_underrun_irq_handler()
401 trace_intel_pch_fifo_underrun(display, pch_transcoder); in intel_pch_fifo_underrun_irq_handler()
402 drm_err(display->drm, "PCH transcoder %c FIFO underrun\n", in intel_pch_fifo_underrun_irq_handler()
416 void intel_check_cpu_fifo_underruns(struct intel_display *display) in intel_check_cpu_fifo_underruns() argument
420 spin_lock_irq(&display->irq.lock); in intel_check_cpu_fifo_underruns()
422 for_each_intel_crtc(display->drm, crtc) { in intel_check_cpu_fifo_underruns()
426 if (HAS_GMCH(display)) in intel_check_cpu_fifo_underruns()
428 else if (DISPLAY_VER(display) == 7) in intel_check_cpu_fifo_underruns()
432 spin_unlock_irq(&display->irq.lock); in intel_check_cpu_fifo_underruns()
443 void intel_check_pch_fifo_underruns(struct intel_display *display) in intel_check_pch_fifo_underruns() argument
447 spin_lock_irq(&display->irq.lock); in intel_check_pch_fifo_underruns()
449 for_each_intel_crtc(display->drm, crtc) { in intel_check_pch_fifo_underruns()
453 if (HAS_PCH_CPT(display)) in intel_check_pch_fifo_underruns()
457 spin_unlock_irq(&display->irq.lock); in intel_check_pch_fifo_underruns()
460 void intel_init_fifo_underrun_reporting(struct intel_display *display, in intel_init_fifo_underrun_reporting() argument
475 if (intel_has_pch_trancoder(display, crtc->pipe)) in intel_init_fifo_underrun_reporting()