Lines Matching refs:pipe
63 enum pipe pipe; in ivb_can_enable_err_int() local
67 for_each_pipe(display, pipe) { in ivb_can_enable_err_int()
68 crtc = intel_crtc_for_pipe(display, pipe); in ivb_can_enable_err_int()
79 enum pipe pipe; in cpt_can_enable_serr_int() local
84 for_each_pipe(display, pipe) { in cpt_can_enable_serr_int()
85 crtc = intel_crtc_for_pipe(display, pipe); in cpt_can_enable_serr_int()
97 i915_reg_t reg = PIPESTAT(display, crtc->pipe); in i9xx_check_fifo_underruns()
105 enable_mask = i915_pipestat_enable_mask(display, crtc->pipe); in i9xx_check_fifo_underruns()
109 trace_intel_cpu_fifo_underrun(display, crtc->pipe); in i9xx_check_fifo_underruns()
110 drm_err(display->drm, "pipe %c underrun\n", pipe_name(crtc->pipe)); in i9xx_check_fifo_underruns()
114 enum pipe pipe, in i9xx_set_fifo_underrun_reporting() argument
117 i915_reg_t reg = PIPESTAT(display, pipe); in i9xx_set_fifo_underrun_reporting()
122 u32 enable_mask = i915_pipestat_enable_mask(display, pipe); in i9xx_set_fifo_underrun_reporting()
130 pipe_name(pipe)); in i9xx_set_fifo_underrun_reporting()
135 enum pipe pipe, bool enable) in ilk_set_fifo_underrun_reporting() argument
137 u32 bit = (pipe == PIPE_A) ? in ilk_set_fifo_underrun_reporting()
149 enum pipe pipe = crtc->pipe; in ivb_check_fifo_underruns() local
154 if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) in ivb_check_fifo_underruns()
157 intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivb_check_fifo_underruns()
160 trace_intel_cpu_fifo_underrun(display, pipe); in ivb_check_fifo_underruns()
161 drm_err(display->drm, "fifo underrun on pipe %c\n", pipe_name(pipe)); in ivb_check_fifo_underruns()
165 enum pipe pipe, bool enable, in ivb_set_fifo_underrun_reporting() argument
170 ERR_INT_FIFO_UNDERRUN(pipe)); in ivb_set_fifo_underrun_reporting()
180 intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivb_set_fifo_underrun_reporting()
183 pipe_name(pipe)); in ivb_set_fifo_underrun_reporting()
189 enum pipe pipe, bool enable) in bdw_set_fifo_underrun_reporting() argument
192 bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN); in bdw_set_fifo_underrun_reporting()
194 bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN); in bdw_set_fifo_underrun_reporting()
198 enum pipe pch_transcoder, in ibx_set_fifo_underrun_reporting()
213 enum pipe pch_transcoder = crtc->pipe; in cpt_check_pch_fifo_underruns()
231 enum pipe pch_transcoder, in cpt_set_fifo_underrun_reporting()
255 enum pipe pipe, bool enable) in __intel_set_cpu_fifo_underrun_reporting() argument
257 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in __intel_set_cpu_fifo_underrun_reporting()
266 i9xx_set_fifo_underrun_reporting(display, pipe, enable, old); in __intel_set_cpu_fifo_underrun_reporting()
268 ilk_set_fifo_underrun_reporting(display, pipe, enable); in __intel_set_cpu_fifo_underrun_reporting()
270 ivb_set_fifo_underrun_reporting(display, pipe, enable, old); in __intel_set_cpu_fifo_underrun_reporting()
272 bdw_set_fifo_underrun_reporting(display, pipe, enable); in __intel_set_cpu_fifo_underrun_reporting()
294 enum pipe pipe, bool enable) in intel_set_cpu_fifo_underrun_reporting() argument
300 ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable); in intel_set_cpu_fifo_underrun_reporting()
321 enum pipe pch_transcoder, in intel_set_pch_fifo_underrun_reporting()
365 enum pipe pipe) in intel_cpu_fifo_underrun_irq_handler() argument
367 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in intel_cpu_fifo_underrun_irq_handler()
378 if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) { in intel_cpu_fifo_underrun_irq_handler()
379 trace_intel_cpu_fifo_underrun(display, pipe); in intel_cpu_fifo_underrun_irq_handler()
381 drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe)); in intel_cpu_fifo_underrun_irq_handler()
397 enum pipe pch_transcoder) in intel_pch_fifo_underrun_irq_handler()
475 if (intel_has_pch_trancoder(display, crtc->pipe)) in intel_init_fifo_underrun_reporting()