Lines Matching refs:flipq
102 struct intel_flipq *flipq = &crtc->flipq[flipq_id]; in intel_flipq_crtc_init() local
104 flipq->start_mmioaddr = intel_pipedmc_start_mmioaddr(crtc) + intel_flipq_offset(flipq_id); in intel_flipq_crtc_init()
105 flipq->flipq_id = flipq_id; in intel_flipq_crtc_init()
109 flipq_id, flipq->start_mmioaddr); in intel_flipq_crtc_init()
186 PIPEDMC_FPQ_PLANEQ_3_TP(crtc->flipq[INTEL_FLIPQ_PLANE_3].tail) | in intel_flipq_write_tail()
187 PIPEDMC_FPQ_PLANEQ_2_TP(crtc->flipq[INTEL_FLIPQ_PLANE_2].tail) | in intel_flipq_write_tail()
188 PIPEDMC_FPQ_PLANEQ_1_TP(crtc->flipq[INTEL_FLIPQ_PLANE_1].tail) | in intel_flipq_write_tail()
189 PIPEDMC_FPQ_FASTQ_TP(crtc->flipq[INTEL_FLIPQ_FAST].tail) | in intel_flipq_write_tail()
190 PIPEDMC_FPQ_GENERALQ_TP(crtc->flipq[INTEL_FLIPQ_GENERAL].tail)); in intel_flipq_write_tail()
212 struct intel_flipq *flipq = &crtc->flipq[flipq_id]; in intel_flipq_dump() local
218 flipq->start_mmioaddr); in intel_flipq_dump()
221 intel_de_read(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, i))); in intel_flipq_dump()
265 struct intel_flipq *flipq = &crtc->flipq[flipq_id]; in intel_flipq_reset() local
270 flipq->tail = 0; in intel_flipq_reset()
332 struct intel_flipq *flipq = &crtc->flipq[flipq_id]; in assert_flipq_has_room() local
338 (flipq->tail + size - head) % size >= size - 1, in assert_flipq_has_room()
341 head, flipq->tail, size); in assert_flipq_has_room()
345 struct intel_flipq *flipq, u32 data, int i) in intel_flipq_write() argument
347 intel_de_write(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, flipq->tail * in intel_flipq_write()
348 intel_flipq_elem_size_dw(flipq->flipq_id) + i), data); in intel_flipq_write()
352 struct intel_flipq *flipq, in lnl_flipq_add() argument
359 switch (flipq->flipq_id) { in lnl_flipq_add()
361 intel_flipq_write(display, flipq, pts, i++); in lnl_flipq_add()
362 intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++); in lnl_flipq_add()
363 intel_flipq_write(display, flipq, LNL_FQ_INTERRUPT | in lnl_flipq_add()
366 intel_flipq_write(display, flipq, 0, i++); in lnl_flipq_add()
367 intel_flipq_write(display, flipq, 0, i++); /* head for second DSB */ in lnl_flipq_add()
368 intel_flipq_write(display, flipq, 0, i++); /* DSB engine + size for second DSB */ in lnl_flipq_add()
373 intel_flipq_write(display, flipq, pts, i++); in lnl_flipq_add()
374 intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++); in lnl_flipq_add()
375 intel_flipq_write(display, flipq, LNL_FQ_INTERRUPT | in lnl_flipq_add()
378 intel_flipq_write(display, flipq, 0, i++); in lnl_flipq_add()
381 MISSING_CASE(flipq->flipq_id); in lnl_flipq_add()
387 struct intel_flipq *flipq, in ptl_flipq_add() argument
394 switch (flipq->flipq_id) { in ptl_flipq_add()
396 intel_flipq_write(display, flipq, pts, i++); in ptl_flipq_add()
397 intel_flipq_write(display, flipq, 0, i++); in ptl_flipq_add()
398 intel_flipq_write(display, flipq, PTL_FQ_INTERRUPT | in ptl_flipq_add()
401 intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++); in ptl_flipq_add()
402 intel_flipq_write(display, flipq, 0, i++); /* DSB engine + size for second DSB */ in ptl_flipq_add()
403 intel_flipq_write(display, flipq, 0, i++); /* head for second DSB */ in ptl_flipq_add()
408 intel_flipq_write(display, flipq, pts, i++); in ptl_flipq_add()
409 intel_flipq_write(display, flipq, 0, i++); in ptl_flipq_add()
410 intel_flipq_write(display, flipq, PTL_FQ_INTERRUPT | in ptl_flipq_add()
413 intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++); in ptl_flipq_add()
416 MISSING_CASE(flipq->flipq_id); in ptl_flipq_add()
428 struct intel_flipq *flipq = &crtc->flipq[flipq_id]; in intel_flipq_add() local
438 ptl_flipq_add(display, flipq, pts, dsb_id, dsb); in intel_flipq_add()
440 lnl_flipq_add(display, flipq, pts, dsb_id, dsb); in intel_flipq_add()
442 flipq->tail = (flipq->tail + 1) % intel_flipq_size_entries(flipq->flipq_id); in intel_flipq_add()