Lines Matching refs:intel_de_write
185 intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe), in intel_flipq_write_tail()
197 intel_de_write(display, PIPEDMC_FPQ_CTL1(crtc->pipe), PIPEDMC_SW_DMC_WAKE); in intel_flipq_sw_dmc_wake()
259 intel_de_write(display, PIPEDMC_FQ_CTRL(pipe), 0); in intel_flipq_reset()
261 intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(pipe), 0); in intel_flipq_reset()
262 intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(pipe), 0); in intel_flipq_reset()
267 intel_de_write(display, PIPEDMC_FPQ_HP(pipe, flipq_id), 0); in intel_flipq_reset()
268 intel_de_write(display, PIPEDMC_FPQ_CHP(pipe, flipq_id), 0); in intel_flipq_reset()
273 intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(pipe), 0); in intel_flipq_reset()
296 intel_de_write(display, PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr), in intel_flipq_enable()
298 intel_de_write(display, PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr), in intel_flipq_enable()
302 intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe), in intel_flipq_enable()
304 intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe), in intel_flipq_enable()
310 intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), PIPEDMC_FQ_CTRL_ENABLE); in intel_flipq_enable()
320 intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), 0); in intel_flipq_disable()
324 intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe), 0); in intel_flipq_disable()
325 intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe), 0); in intel_flipq_disable()
347 intel_de_write(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, flipq->tail * in intel_flipq_write()