Lines Matching refs:display
26 static void vlv_steal_power_sequencer(struct intel_display *display,
34 struct intel_display *display = to_intel_display(intel_dp); in pps_name() local
37 if (display->platform.valleyview || display->platform.cherryview) { in pps_name()
70 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_lock() local
76 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); in intel_pps_lock()
77 mutex_lock(&display->pps.mutex); in intel_pps_lock()
85 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_unlock() local
87 mutex_unlock(&display->pps.mutex); in intel_pps_unlock()
88 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); in intel_pps_unlock()
96 struct intel_display *display = to_intel_display(intel_dp); in vlv_power_sequencer_kick() local
104 if (drm_WARN(display->drm, in vlv_power_sequencer_kick()
105 intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN, in vlv_power_sequencer_kick()
111 drm_dbg_kms(display->drm, in vlv_power_sequencer_kick()
119 DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
124 if (display->platform.cherryview) in vlv_power_sequencer_kick()
129 pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
136 release_cl_override = display->platform.cherryview && in vlv_power_sequencer_kick()
137 !chv_phy_powergate_ch(display, phy, ch, true); in vlv_power_sequencer_kick()
139 if (vlv_force_pll_on(display, pipe, vlv_get_dpll(display))) { in vlv_power_sequencer_kick()
140 drm_err(display->drm, in vlv_power_sequencer_kick()
153 intel_de_write(display, intel_dp->output_reg, DP); in vlv_power_sequencer_kick()
154 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
156 intel_de_write(display, intel_dp->output_reg, DP | DP_PORT_EN); in vlv_power_sequencer_kick()
157 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
159 intel_de_write(display, intel_dp->output_reg, DP & ~DP_PORT_EN); in vlv_power_sequencer_kick()
160 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
163 vlv_force_pll_off(display, pipe); in vlv_power_sequencer_kick()
166 chv_phy_powergate_ch(display, phy, ch, false); in vlv_power_sequencer_kick()
170 static enum pipe vlv_find_free_pps(struct intel_display *display) in vlv_find_free_pps() argument
179 for_each_intel_dp(display->drm, encoder) { in vlv_find_free_pps()
183 drm_WARN_ON(display->drm, in vlv_find_free_pps()
191 drm_WARN_ON(display->drm, in vlv_find_free_pps()
208 struct intel_display *display = to_intel_display(intel_dp); in vlv_power_sequencer_pipe() local
212 lockdep_assert_held(&display->pps.mutex); in vlv_power_sequencer_pipe()
215 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp)); in vlv_power_sequencer_pipe()
217 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE && in vlv_power_sequencer_pipe()
223 pipe = vlv_find_free_pps(display); in vlv_power_sequencer_pipe()
229 if (drm_WARN_ON(display->drm, pipe == INVALID_PIPE)) in vlv_power_sequencer_pipe()
232 vlv_steal_power_sequencer(display, pipe); in vlv_power_sequencer_pipe()
235 drm_dbg_kms(display->drm, in vlv_power_sequencer_pipe()
256 struct intel_display *display = to_intel_display(intel_dp); in bxt_power_sequencer_idx() local
259 lockdep_assert_held(&display->pps.mutex); in bxt_power_sequencer_idx()
262 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp)); in bxt_power_sequencer_idx()
278 typedef bool (*pps_check)(struct intel_display *display, int pps_idx);
280 static bool pps_has_pp_on(struct intel_display *display, int pps_idx) in pps_has_pp_on() argument
282 return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON; in pps_has_pp_on()
285 static bool pps_has_vdd_on(struct intel_display *display, int pps_idx) in pps_has_vdd_on() argument
287 return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD; in pps_has_vdd_on()
290 static bool pps_any(struct intel_display *display, int pps_idx) in pps_any() argument
296 vlv_initial_pps_pipe(struct intel_display *display, in vlv_initial_pps_pipe() argument
302 u32 port_sel = intel_de_read(display, in vlv_initial_pps_pipe()
303 PP_ON_DELAYS(display, pipe)) & in vlv_initial_pps_pipe()
309 if (!check(display, pipe)) in vlv_initial_pps_pipe()
321 struct intel_display *display = to_intel_display(intel_dp); in vlv_initial_power_sequencer_setup() local
325 lockdep_assert_held(&display->pps.mutex); in vlv_initial_power_sequencer_setup()
329 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
333 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
337 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
342 drm_dbg_kms(display->drm, in vlv_initial_power_sequencer_setup()
348 drm_dbg_kms(display->drm, in vlv_initial_power_sequencer_setup()
354 static int intel_num_pps(struct intel_display *display) in intel_num_pps() argument
356 if (display->platform.valleyview || display->platform.cherryview) in intel_num_pps()
359 if (display->platform.geminilake || display->platform.broxton) in intel_num_pps()
362 if (INTEL_PCH_TYPE(display) >= PCH_MTL) in intel_num_pps()
365 if (INTEL_PCH_TYPE(display) >= PCH_DG1) in intel_num_pps()
368 if (INTEL_PCH_TYPE(display) >= PCH_ICP) in intel_num_pps()
376 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_is_valid() local
379 INTEL_PCH_TYPE(display) >= PCH_ICP && in intel_pps_is_valid()
380 INTEL_PCH_TYPE(display) <= PCH_ADP) in intel_pps_is_valid()
381 return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT; in intel_pps_is_valid()
387 bxt_initial_pps_idx(struct intel_display *display, pps_check check) in bxt_initial_pps_idx() argument
389 int pps_idx, pps_num = intel_num_pps(display); in bxt_initial_pps_idx()
392 if (check(display, pps_idx)) in bxt_initial_pps_idx()
402 struct intel_display *display = to_intel_display(intel_dp); in pps_initial_setup() local
406 lockdep_assert_held(&display->pps.mutex); in pps_initial_setup()
408 if (display->platform.valleyview || display->platform.cherryview) { in pps_initial_setup()
414 if (intel_num_pps(display) > 1) in pps_initial_setup()
419 if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display))) in pps_initial_setup()
424 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on); in pps_initial_setup()
427 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on); in pps_initial_setup()
430 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any); in pps_initial_setup()
432 drm_dbg_kms(display->drm, in pps_initial_setup()
437 drm_dbg_kms(display->drm, in pps_initial_setup()
446 void vlv_pps_reset_all(struct intel_display *display) in vlv_pps_reset_all() argument
450 if (!HAS_DISPLAY(display)) in vlv_pps_reset_all()
463 for_each_intel_dp(display->drm, encoder) { in vlv_pps_reset_all()
466 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE); in vlv_pps_reset_all()
473 void bxt_pps_reset_all(struct intel_display *display) in bxt_pps_reset_all() argument
477 if (!HAS_DISPLAY(display)) in bxt_pps_reset_all()
482 for_each_intel_dp(display->drm, encoder) { in bxt_pps_reset_all()
501 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_get_registers() local
506 if (display->platform.valleyview || display->platform.cherryview) in intel_pps_get_registers()
508 else if (display->platform.geminilake || display->platform.broxton) in intel_pps_get_registers()
513 regs->pp_ctrl = PP_CONTROL(display, pps_idx); in intel_pps_get_registers()
514 regs->pp_stat = PP_STATUS(display, pps_idx); in intel_pps_get_registers()
515 regs->pp_on = PP_ON_DELAYS(display, pps_idx); in intel_pps_get_registers()
516 regs->pp_off = PP_OFF_DELAYS(display, pps_idx); in intel_pps_get_registers()
519 if (display->platform.geminilake || display->platform.broxton || in intel_pps_get_registers()
520 INTEL_PCH_TYPE(display) >= PCH_CNP) in intel_pps_get_registers()
523 regs->pp_div = PP_DIVISOR(display, pps_idx); in intel_pps_get_registers()
548 struct intel_display *display = to_intel_display(intel_dp); in edp_have_panel_power() local
550 lockdep_assert_held(&display->pps.mutex); in edp_have_panel_power()
552 if ((display->platform.valleyview || display->platform.cherryview) && in edp_have_panel_power()
556 return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power()
561 struct intel_display *display = to_intel_display(intel_dp); in edp_have_panel_vdd() local
563 lockdep_assert_held(&display->pps.mutex); in edp_have_panel_vdd()
565 if ((display->platform.valleyview || display->platform.cherryview) && in edp_have_panel_vdd()
569 return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; in edp_have_panel_vdd()
574 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_check_power_unlocked() local
581 drm_WARN(display->drm, 1, in intel_pps_check_power_unlocked()
585 drm_dbg_kms(display->drm, in intel_pps_check_power_unlocked()
589 intel_de_read(display, _pp_stat_reg(intel_dp)), in intel_pps_check_power_unlocked()
590 intel_de_read(display, _pp_ctrl_reg(intel_dp))); in intel_pps_check_power_unlocked()
608 struct intel_display *display = to_intel_display(intel_dp); in wait_panel_status() local
612 lockdep_assert_held(&display->pps.mutex); in wait_panel_status()
619 drm_dbg_kms(display->drm, in wait_panel_status()
624 intel_de_read(display, pp_stat_reg), in wait_panel_status()
625 intel_de_read(display, pp_ctrl_reg)); in wait_panel_status()
627 if (intel_de_wait(display, pp_stat_reg, mask, value, 5000)) in wait_panel_status()
628 drm_err(display->drm, in wait_panel_status()
632 intel_de_read(display, pp_stat_reg), in wait_panel_status()
633 intel_de_read(display, pp_ctrl_reg)); in wait_panel_status()
635 drm_dbg_kms(display->drm, "Wait complete\n"); in wait_panel_status()
640 struct intel_display *display = to_intel_display(intel_dp); in wait_panel_on() local
643 drm_dbg_kms(display->drm, in wait_panel_on()
652 struct intel_display *display = to_intel_display(intel_dp); in wait_panel_off() local
655 drm_dbg_kms(display->drm, in wait_panel_off()
664 struct intel_display *display = to_intel_display(intel_dp); in wait_panel_power_cycle() local
676 drm_dbg_kms(display->drm, in wait_panel_power_cycle()
718 struct intel_display *display = to_intel_display(intel_dp); in ilk_get_pp_control() local
721 lockdep_assert_held(&display->pps.mutex); in ilk_get_pp_control()
723 control = intel_de_read(display, _pp_ctrl_reg(intel_dp)); in ilk_get_pp_control()
724 if (drm_WARN_ON(display->drm, !HAS_DDI(display) && in ilk_get_pp_control()
739 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_vdd_on_unlocked() local
748 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_on_unlocked()
756 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref); in intel_pps_vdd_on_unlocked()
757 intel_dp->pps.vdd_wakeref = intel_display_power_get(display, in intel_pps_vdd_on_unlocked()
763 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD on\n", in intel_pps_vdd_on_unlocked()
773 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_vdd_on_unlocked()
774 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_vdd_on_unlocked()
775 drm_dbg_kms(display->drm, in intel_pps_vdd_on_unlocked()
779 intel_de_read(display, pp_stat_reg), in intel_pps_vdd_on_unlocked()
780 intel_de_read(display, pp_ctrl_reg)); in intel_pps_vdd_on_unlocked()
785 drm_dbg_kms(display->drm, in intel_pps_vdd_on_unlocked()
804 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_vdd_on() local
814 INTEL_DISPLAY_STATE_WARN(display, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n", in intel_pps_vdd_on()
822 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_vdd_off_sync_unlocked() local
827 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_off_sync_unlocked()
829 drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd); in intel_pps_vdd_off_sync_unlocked()
834 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD off\n", in intel_pps_vdd_off_sync_unlocked()
844 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_vdd_off_sync_unlocked()
845 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_vdd_off_sync_unlocked()
848 drm_dbg_kms(display->drm, in intel_pps_vdd_off_sync_unlocked()
852 intel_de_read(display, pp_stat_reg), in intel_pps_vdd_off_sync_unlocked()
853 intel_de_read(display, pp_ctrl_reg)); in intel_pps_vdd_off_sync_unlocked()
860 intel_display_power_put(display, in intel_pps_vdd_off_sync_unlocked()
896 struct intel_display *display = to_intel_display(intel_dp); in edp_panel_vdd_schedule_off() local
912 queue_delayed_work(display->wq.unordered, in edp_panel_vdd_schedule_off()
923 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_vdd_off_unlocked() local
928 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_off_unlocked()
930 INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd, in intel_pps_vdd_off_unlocked()
957 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_on_unlocked() local
961 lockdep_assert_held(&display->pps.mutex); in intel_pps_on_unlocked()
966 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power on\n", in intel_pps_on_unlocked()
971 if (drm_WARN(display->drm, edp_have_panel_power(intel_dp), in intel_pps_on_unlocked()
982 if (display->platform.ironlake) { in intel_pps_on_unlocked()
985 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
986 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
993 if (IS_DISPLAY_VER(display, 13, 14)) in intel_pps_on_unlocked()
994 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in intel_pps_on_unlocked()
998 if (!display->platform.ironlake) in intel_pps_on_unlocked()
1001 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
1002 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1007 if (IS_DISPLAY_VER(display, 13, 14)) in intel_pps_on_unlocked()
1008 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in intel_pps_on_unlocked()
1011 if (display->platform.ironlake) { in intel_pps_on_unlocked()
1013 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
1014 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1031 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_off_unlocked() local
1036 lockdep_assert_held(&display->pps.mutex); in intel_pps_off_unlocked()
1041 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power off\n", in intel_pps_off_unlocked()
1045 drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd, in intel_pps_off_unlocked()
1060 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_off_unlocked()
1061 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_off_unlocked()
1069 intel_display_power_put(display, in intel_pps_off_unlocked()
1088 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_backlight_on() local
1106 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_backlight_on()
1107 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_backlight_on()
1114 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_backlight_off() local
1127 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_backlight_off()
1128 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_backlight_off()
1141 struct intel_display *display = to_intel_display(connector); in intel_pps_backlight_power() local
1152 drm_dbg_kms(display->drm, "panel power control backlight %s\n", in intel_pps_backlight_power()
1163 struct intel_display *display = to_intel_display(intel_dp); in vlv_detach_power_sequencer() local
1166 i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe); in vlv_detach_power_sequencer()
1168 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE); in vlv_detach_power_sequencer()
1170 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
1184 drm_dbg_kms(display->drm, in vlv_detach_power_sequencer()
1188 intel_de_write(display, pp_on_reg, 0); in vlv_detach_power_sequencer()
1189 intel_de_posting_read(display, pp_on_reg); in vlv_detach_power_sequencer()
1194 static void vlv_steal_power_sequencer(struct intel_display *display, in vlv_steal_power_sequencer() argument
1199 lockdep_assert_held(&display->pps.mutex); in vlv_steal_power_sequencer()
1201 for_each_intel_dp(display->drm, encoder) { in vlv_steal_power_sequencer()
1204 drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe, in vlv_steal_power_sequencer()
1212 drm_dbg_kms(display->drm, in vlv_steal_power_sequencer()
1224 struct intel_display *display = to_intel_display(intel_dp); in vlv_active_pipe() local
1228 if (g4x_dp_port_enabled(display, intel_dp->output_reg, in vlv_active_pipe()
1275 struct intel_display *display = to_intel_display(encoder); in vlv_pps_port_enable_unlocked() local
1279 lockdep_assert_held(&display->pps.mutex); in vlv_pps_port_enable_unlocked()
1281 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE); in vlv_pps_port_enable_unlocked()
1297 vlv_steal_power_sequencer(display, crtc->pipe); in vlv_pps_port_enable_unlocked()
1307 drm_dbg_kms(display->drm, in vlv_pps_port_enable_unlocked()
1331 struct intel_display *display = to_intel_display(intel_dp); in pps_vdd_init() local
1334 lockdep_assert_held(&display->pps.mutex); in pps_vdd_init()
1345 drm_dbg_kms(display->drm, in pps_vdd_init()
1349 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref); in pps_vdd_init()
1350 intel_dp->pps.vdd_wakeref = intel_display_power_get(display, in pps_vdd_init()
1383 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_readout_hw_state() local
1392 if (!HAS_DDI(display)) in intel_pps_readout_hw_state()
1393 intel_de_write(display, regs.pp_ctrl, pp_ctl); in intel_pps_readout_hw_state()
1395 pp_on = intel_de_read(display, regs.pp_on); in intel_pps_readout_hw_state()
1396 pp_off = intel_de_read(display, regs.pp_off); in intel_pps_readout_hw_state()
1407 pp_div = intel_de_read(display, regs.pp_div); in intel_pps_readout_hw_state()
1422 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_dump_state() local
1424 drm_dbg_kms(display->drm, in intel_pps_dump_state()
1433 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_verify_state() local
1444 drm_err(display->drm, "PPS state mismatch\n"); in intel_pps_verify_state()
1471 struct intel_display *display = to_intel_display(intel_dp); in pps_init_delays_bios() local
1473 lockdep_assert_held(&display->pps.mutex); in pps_init_delays_bios()
1486 struct intel_display *display = to_intel_display(intel_dp); in pps_init_delays_vbt() local
1500 if (intel_has_quirk(display, QUIRK_INCREASE_T12_DELAY)) { in pps_init_delays_vbt()
1502 drm_dbg_kms(display->drm, in pps_init_delays_vbt()
1513 struct intel_display *display = to_intel_display(intel_dp); in pps_init_delays_spec() local
1515 lockdep_assert_held(&display->pps.mutex); in pps_init_delays_spec()
1529 struct intel_display *display = to_intel_display(intel_dp); in pps_init_delays() local
1533 lockdep_assert_held(&display->pps.mutex); in pps_init_delays()
1561 drm_dbg_kms(display->drm, in pps_init_delays()
1567 drm_dbg_kms(display->drm, "backlight on delay %d, off delay %d\n", in pps_init_delays()
1591 struct intel_display *display = to_intel_display(intel_dp); in pps_init_registers() local
1593 int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000; in pps_init_registers()
1598 lockdep_assert_held(&display->pps.mutex); in pps_init_registers()
1617 drm_WARN(display->drm, pp & PANEL_POWER_ON, in pps_init_registers()
1621 drm_dbg_kms(display->drm, in pps_init_registers()
1626 intel_de_write(display, regs.pp_ctrl, pp); in pps_init_registers()
1636 if (display->platform.valleyview || display->platform.cherryview) { in pps_init_registers()
1638 } else if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) { in pps_init_registers()
1657 intel_de_write(display, regs.pp_on, pp_on); in pps_init_registers()
1658 intel_de_write(display, regs.pp_off, pp_off); in pps_init_registers()
1664 intel_de_write(display, regs.pp_div, in pps_init_registers()
1670 intel_de_rmw(display, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK, in pps_init_registers()
1674 drm_dbg_kms(display->drm, in pps_init_registers()
1676 intel_de_read(display, regs.pp_on), in pps_init_registers()
1677 intel_de_read(display, regs.pp_off), in pps_init_registers()
1679 intel_de_read(display, regs.pp_div) : in pps_init_registers()
1680 (intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); in pps_init_registers()
1685 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_encoder_reset() local
1696 if (display->platform.valleyview || display->platform.cherryview) in intel_pps_encoder_reset()
1731 struct intel_display *display = to_intel_display(intel_dp); in pps_init_late() local
1735 if (display->platform.valleyview || display->platform.cherryview) in pps_init_late()
1738 if (intel_num_pps(display) < 2) in pps_init_late()
1741 drm_WARN(display->drm, in pps_init_late()
1771 void intel_pps_unlock_regs_wa(struct intel_display *display) in intel_pps_unlock_regs_wa() argument
1776 if (!HAS_DISPLAY(display) || HAS_DDI(display)) in intel_pps_unlock_regs_wa()
1782 pps_num = intel_num_pps(display); in intel_pps_unlock_regs_wa()
1785 intel_de_rmw(display, PP_CONTROL(display, pps_idx), in intel_pps_unlock_regs_wa()
1789 void intel_pps_setup(struct intel_display *display) in intel_pps_setup() argument
1791 if (HAS_PCH_SPLIT(display) || display->platform.geminilake || display->platform.broxton) in intel_pps_setup()
1792 display->pps.mmio_base = PCH_PPS_BASE; in intel_pps_setup()
1793 else if (display->platform.valleyview || display->platform.cherryview) in intel_pps_setup()
1794 display->pps.mmio_base = VLV_PPS_BASE; in intel_pps_setup()
1796 display->pps.mmio_base = PPS_BASE; in intel_pps_setup()
1832 void assert_pps_unlocked(struct intel_display *display, enum pipe pipe) in assert_pps_unlocked() argument
1839 if (drm_WARN_ON(display->drm, HAS_DDI(display))) in assert_pps_unlocked()
1842 if (HAS_PCH_SPLIT(display)) { in assert_pps_unlocked()
1845 pp_reg = PP_CONTROL(display, 0); in assert_pps_unlocked()
1846 port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) & in assert_pps_unlocked()
1851 intel_lvds_port_enabled(display, PCH_LVDS, &panel_pipe); in assert_pps_unlocked()
1854 g4x_dp_port_enabled(display, DP_A, PORT_A, &panel_pipe); in assert_pps_unlocked()
1857 g4x_dp_port_enabled(display, PCH_DP_C, PORT_C, &panel_pipe); in assert_pps_unlocked()
1860 g4x_dp_port_enabled(display, PCH_DP_D, PORT_D, &panel_pipe); in assert_pps_unlocked()
1866 } else if (display->platform.valleyview || display->platform.cherryview) { in assert_pps_unlocked()
1868 pp_reg = PP_CONTROL(display, pipe); in assert_pps_unlocked()
1873 pp_reg = PP_CONTROL(display, 0); in assert_pps_unlocked()
1874 port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) & in assert_pps_unlocked()
1877 drm_WARN_ON(display->drm, in assert_pps_unlocked()
1879 intel_lvds_port_enabled(display, LVDS, &panel_pipe); in assert_pps_unlocked()
1882 val = intel_de_read(display, pp_reg); in assert_pps_unlocked()
1887 INTEL_DISPLAY_STATE_WARN(display, panel_pipe == pipe && locked, in assert_pps_unlocked()