Lines Matching refs:pps
35 struct intel_pps *pps = &intel_dp->pps; in pps_name() local
38 switch (pps->vlv_pps_pipe) { in pps_name()
50 MISSING_CASE(pps->vlv_pps_pipe); in pps_name()
54 switch (pps->pps_idx) { in pps_name()
60 MISSING_CASE(pps->pps_idx); in pps_name()
77 mutex_lock(&display->pps.mutex); in intel_pps_lock()
87 mutex_unlock(&display->pps.mutex); in intel_pps_unlock()
98 enum pipe pipe = intel_dp->pps.vlv_pps_pipe; in vlv_power_sequencer_kick()
184 intel_dp->pps.vlv_active_pipe != INVALID_PIPE && in vlv_find_free_pps()
185 intel_dp->pps.vlv_active_pipe != in vlv_find_free_pps()
186 intel_dp->pps.vlv_pps_pipe); in vlv_find_free_pps()
188 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE) in vlv_find_free_pps()
189 pipes &= ~(1 << intel_dp->pps.vlv_pps_pipe); in vlv_find_free_pps()
192 intel_dp->pps.vlv_pps_pipe != INVALID_PIPE); in vlv_find_free_pps()
194 if (intel_dp->pps.vlv_active_pipe != INVALID_PIPE) in vlv_find_free_pps()
195 pipes &= ~(1 << intel_dp->pps.vlv_active_pipe); in vlv_find_free_pps()
212 lockdep_assert_held(&display->pps.mutex); in vlv_power_sequencer_pipe()
217 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE && in vlv_power_sequencer_pipe()
218 intel_dp->pps.vlv_active_pipe != intel_dp->pps.vlv_pps_pipe); in vlv_power_sequencer_pipe()
220 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE) in vlv_power_sequencer_pipe()
221 return intel_dp->pps.vlv_pps_pipe; in vlv_power_sequencer_pipe()
233 intel_dp->pps.vlv_pps_pipe = pipe; in vlv_power_sequencer_pipe()
250 return intel_dp->pps.vlv_pps_pipe; in vlv_power_sequencer_pipe()
257 int pps_idx = intel_dp->pps.pps_idx; in bxt_power_sequencer_idx()
259 lockdep_assert_held(&display->pps.mutex); in bxt_power_sequencer_idx()
264 if (!intel_dp->pps.bxt_pps_reset) in bxt_power_sequencer_idx()
267 intel_dp->pps.bxt_pps_reset = false; in bxt_power_sequencer_idx()
325 lockdep_assert_held(&display->pps.mutex); in vlv_initial_power_sequencer_setup()
329 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
332 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) in vlv_initial_power_sequencer_setup()
333 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
336 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) in vlv_initial_power_sequencer_setup()
337 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
341 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) { in vlv_initial_power_sequencer_setup()
378 if (intel_dp->pps.pps_idx == 1 && in intel_pps_is_valid()
406 lockdep_assert_held(&display->pps.mutex); in pps_initial_setup()
415 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller; in pps_initial_setup()
417 intel_dp->pps.pps_idx = 0; in pps_initial_setup()
419 if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display))) in pps_initial_setup()
420 intel_dp->pps.pps_idx = -1; in pps_initial_setup()
423 if (intel_dp->pps.pps_idx < 0) in pps_initial_setup()
424 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on); in pps_initial_setup()
426 if (intel_dp->pps.pps_idx < 0) in pps_initial_setup()
427 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on); in pps_initial_setup()
429 if (intel_dp->pps.pps_idx < 0) { in pps_initial_setup()
430 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any); in pps_initial_setup()
466 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE); in vlv_pps_reset_all()
469 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE; in vlv_pps_reset_all()
486 intel_dp->pps.bxt_pps_reset = true; in bxt_pps_reset_all()
511 pps_idx = intel_dp->pps.pps_idx; in intel_pps_get_registers()
550 lockdep_assert_held(&display->pps.mutex); in edp_have_panel_power()
553 intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) in edp_have_panel_power()
563 lockdep_assert_held(&display->pps.mutex); in edp_have_panel_vdd()
566 intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) in edp_have_panel_vdd()
612 lockdep_assert_held(&display->pps.mutex); in wait_panel_status()
672 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time); in wait_panel_power_cycle()
674 remaining = max(0, intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration); in wait_panel_power_cycle()
702 wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on, in wait_backlight_on()
703 intel_dp->pps.backlight_on_delay); in wait_backlight_on()
708 wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off, in edp_wait_backlight_off()
709 intel_dp->pps.backlight_off_delay); in edp_wait_backlight_off()
721 lockdep_assert_held(&display->pps.mutex); in ilk_get_pp_control()
743 bool need_to_disable = !intel_dp->pps.want_panel_vdd; in intel_pps_vdd_on_unlocked()
748 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_on_unlocked()
750 cancel_delayed_work(&intel_dp->pps.panel_vdd_work); in intel_pps_vdd_on_unlocked()
751 intel_dp->pps.want_panel_vdd = true; in intel_pps_vdd_on_unlocked()
756 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref); in intel_pps_vdd_on_unlocked()
757 intel_dp->pps.vdd_wakeref = intel_display_power_get(display, in intel_pps_vdd_on_unlocked()
789 msleep(intel_dp->pps.panel_power_up_delay); in intel_pps_vdd_on_unlocked()
827 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_off_sync_unlocked()
829 drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd); in intel_pps_vdd_off_sync_unlocked()
856 intel_dp->pps.panel_power_off_time = ktime_get_boottime(); in intel_pps_vdd_off_sync_unlocked()
862 fetch_and_zero(&intel_dp->pps.vdd_wakeref)); in intel_pps_vdd_off_sync_unlocked()
872 cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work); in intel_pps_vdd_off_sync()
883 struct intel_pps *pps = container_of(to_delayed_work(__work), in edp_panel_vdd_work() local
885 struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps); in edp_panel_vdd_work()
889 if (!intel_dp->pps.want_panel_vdd) in edp_panel_vdd_work()
903 if (intel_dp->pps.initializing) in edp_panel_vdd_schedule_off()
911 delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5); in edp_panel_vdd_schedule_off()
913 &intel_dp->pps.panel_vdd_work, delay); in edp_panel_vdd_schedule_off()
928 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_off_unlocked()
930 INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd, in intel_pps_vdd_off_unlocked()
936 intel_dp->pps.want_panel_vdd = false; in intel_pps_vdd_off_unlocked()
961 lockdep_assert_held(&display->pps.mutex); in intel_pps_on_unlocked()
1005 intel_dp->pps.last_power_on = jiffies; in intel_pps_on_unlocked()
1036 lockdep_assert_held(&display->pps.mutex); in intel_pps_off_unlocked()
1045 drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd, in intel_pps_off_unlocked()
1058 intel_dp->pps.want_panel_vdd = false; in intel_pps_off_unlocked()
1064 intel_dp->pps.panel_power_off_time = ktime_get_boottime(); in intel_pps_off_unlocked()
1071 fetch_and_zero(&intel_dp->pps.vdd_wakeref)); in intel_pps_off_unlocked()
1131 intel_dp->pps.last_backlight_off = jiffies; in intel_pps_backlight_off()
1165 enum pipe pipe = intel_dp->pps.vlv_pps_pipe; in vlv_detach_power_sequencer()
1168 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE); in vlv_detach_power_sequencer()
1191 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE; in vlv_detach_power_sequencer()
1199 lockdep_assert_held(&display->pps.mutex); in vlv_steal_power_sequencer()
1204 drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe, in vlv_steal_power_sequencer()
1209 if (intel_dp->pps.vlv_pps_pipe != pipe) in vlv_steal_power_sequencer()
1238 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE; in vlv_pps_pipe_init()
1239 intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp); in vlv_pps_pipe_init()
1248 intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp); in vlv_pps_pipe_reset()
1263 pipe = intel_dp->pps.vlv_pps_pipe; in vlv_pps_backlight_initial_pipe()
1279 lockdep_assert_held(&display->pps.mutex); in vlv_pps_port_enable_unlocked()
1281 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE); in vlv_pps_port_enable_unlocked()
1283 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE && in vlv_pps_port_enable_unlocked()
1284 intel_dp->pps.vlv_pps_pipe != crtc->pipe) { in vlv_pps_port_enable_unlocked()
1299 intel_dp->pps.vlv_active_pipe = crtc->pipe; in vlv_pps_port_enable_unlocked()
1305 intel_dp->pps.vlv_pps_pipe = crtc->pipe; in vlv_pps_port_enable_unlocked()
1326 intel_dp->pps.vlv_active_pipe = INVALID_PIPE; in vlv_pps_port_disable()
1334 lockdep_assert_held(&display->pps.mutex); in pps_vdd_init()
1349 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref); in pps_vdd_init()
1350 intel_dp->pps.vdd_wakeref = intel_display_power_get(display, in pps_vdd_init()
1375 intel_dp->pps.panel_power_off_time = 0; in pps_init_timestamps()
1376 intel_dp->pps.last_power_on = jiffies; in pps_init_timestamps()
1377 intel_dp->pps.last_backlight_off = jiffies; in pps_init_timestamps()
1435 struct intel_pps_delays *sw = &intel_dp->pps.pps_delays; in intel_pps_verify_state()
1473 lockdep_assert_held(&display->pps.mutex); in pps_init_delays_bios()
1475 if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays)) in pps_init_delays_bios()
1476 intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays); in pps_init_delays_bios()
1478 *bios = intel_dp->pps.bios_pps_delays; in pps_init_delays_bios()
1489 *vbt = connector->panel.vbt.edp.pps; in pps_init_delays_vbt()
1515 lockdep_assert_held(&display->pps.mutex); in pps_init_delays_spec()
1531 *final = &intel_dp->pps.pps_delays; in pps_init_delays()
1533 lockdep_assert_held(&display->pps.mutex); in pps_init_delays()
1555 intel_dp->pps.panel_power_up_delay = pps_units_to_msecs(final->power_up); in pps_init_delays()
1556 intel_dp->pps.backlight_on_delay = pps_units_to_msecs(final->backlight_on); in pps_init_delays()
1557 intel_dp->pps.backlight_off_delay = pps_units_to_msecs(final->backlight_off); in pps_init_delays()
1558 intel_dp->pps.panel_power_down_delay = pps_units_to_msecs(final->power_down); in pps_init_delays()
1559 intel_dp->pps.panel_power_cycle_delay = pps_units_to_msecs(final->power_cycle); in pps_init_delays()
1563 intel_dp->pps.panel_power_up_delay, in pps_init_delays()
1564 intel_dp->pps.panel_power_down_delay, in pps_init_delays()
1565 intel_dp->pps.panel_power_cycle_delay); in pps_init_delays()
1568 intel_dp->pps.backlight_on_delay, in pps_init_delays()
1569 intel_dp->pps.backlight_off_delay); in pps_init_delays()
1596 const struct intel_pps_delays *seq = &intel_dp->pps.pps_delays; in pps_init_registers()
1598 lockdep_assert_held(&display->pps.mutex); in pps_init_registers()
1713 intel_dp->pps.initializing = true; in intel_pps_init()
1714 INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); in intel_pps_init()
1743 intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller, in pps_init_late()
1746 intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller); in pps_init_late()
1749 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller; in pps_init_late()
1760 memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays)); in intel_pps_init_late()
1764 intel_dp->pps.initializing = false; in intel_pps_init_late()
1792 display->pps.mmio_base = PCH_PPS_BASE; in intel_pps_setup()
1794 display->pps.mmio_base = VLV_PPS_BASE; in intel_pps_setup()
1796 display->pps.mmio_base = PPS_BASE; in intel_pps_setup()
1808 intel_dp->pps.panel_power_up_delay); in intel_pps_show()
1810 intel_dp->pps.panel_power_down_delay); in intel_pps_show()
1812 intel_dp->pps.panel_power_cycle_delay); in intel_pps_show()
1814 intel_dp->pps.backlight_on_delay); in intel_pps_show()
1816 intel_dp->pps.backlight_off_delay); in intel_pps_show()