Lines Matching refs:intel_de_read
272 lane_mask = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia)); in intel_tc_port_get_lane_mask()
287 pin_mask = intel_de_read(display, PORT_TX_DFLEXPA1(tc->phy_fia)); in intel_tc_port_get_pin_assignment_mask()
304 val = intel_de_read(display, TCSS_DDI_STATUS(tc_port)); in lnl_tc_port_get_max_lane_count()
403 val = intel_de_read(display, PORT_TX_DFLEXDPMLE1(tc->phy_fia)); in intel_tc_port_set_fia_lane_count()
499 fia_isr = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia)); in icl_tc_phy_hpd_live_status()
500 pch_isr = intel_de_read(display, SDEISR); in icl_tc_phy_hpd_live_status()
536 val = intel_de_read(display, PORT_TX_DFLEXDPPMS(tc->phy_fia)); in icl_tc_phy_is_ready()
555 val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia)); in icl_tc_phy_take_ownership()
580 val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia)); in icl_tc_phy_is_owned()
737 val = intel_de_read(display, PORT_TX_DFLEXDPSP(FIA1)); in tgl_tc_phy_init()
784 cpu_isr = intel_de_read(display, GEN11_DE_HPD_ISR); in adlp_tc_phy_hpd_live_status()
785 pch_isr = intel_de_read(display, SDEISR); in adlp_tc_phy_hpd_live_status()
814 val = intel_de_read(display, TCSS_DDI_STATUS(tc_port)); in adlp_tc_phy_is_ready()
847 val = intel_de_read(display, DDI_BUF_CTL(port)); in adlp_tc_phy_is_owned()
972 pica_isr = intel_de_read(display, PICAINTERRUPT_ISR); in xelpdp_tc_phy_hpd_live_status()
973 pch_isr = intel_de_read(display, SDEISR); in xelpdp_tc_phy_hpd_live_status()
996 return intel_de_read(display, reg) & XELPDP_TCSS_POWER_STATE; in xelpdp_tc_phy_tcss_power_is_enabled()
1055 val = intel_de_read(display, reg); in __xelpdp_tc_phy_enable_tcss_power()
1099 val = intel_de_read(display, reg); in xelpdp_tc_phy_take_ownership()
1115 return intel_de_read(display, reg) & XELPDP_TC_PHY_OWNERSHIP; in xelpdp_tc_phy_is_owned()
1491 return intel_de_read(display, DDI_BUF_CTL(dig_port->base.port)) & in tc_port_is_enabled()