Lines Matching refs:pps_temp
882 u32 pps_temp; in intel_dsc_get_pps_config() local
885 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0); in intel_dsc_get_pps_config()
887 vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp); in intel_dsc_get_pps_config()
888 vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp); in intel_dsc_get_pps_config()
889 vdsc_cfg->block_pred_enable = pps_temp & DSC_PPS0_BLOCK_PREDICTION; in intel_dsc_get_pps_config()
890 vdsc_cfg->convert_rgb = pps_temp & DSC_PPS0_COLOR_SPACE_CONVERSION; in intel_dsc_get_pps_config()
891 vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE; in intel_dsc_get_pps_config()
892 vdsc_cfg->native_422 = pps_temp & DSC_PPS0_NATIVE_422_ENABLE; in intel_dsc_get_pps_config()
893 vdsc_cfg->native_420 = pps_temp & DSC_PPS0_NATIVE_420_ENABLE; in intel_dsc_get_pps_config()
894 vdsc_cfg->vbr_enable = pps_temp & DSC_PPS0_VBR_ENABLE; in intel_dsc_get_pps_config()
897 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1); in intel_dsc_get_pps_config()
899 vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp); in intel_dsc_get_pps_config()
907 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2); in intel_dsc_get_pps_config()
909 vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) * num_vdsc_instances; in intel_dsc_get_pps_config()
910 vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp); in intel_dsc_get_pps_config()
913 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3); in intel_dsc_get_pps_config()
915 vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp); in intel_dsc_get_pps_config()
916 vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp); in intel_dsc_get_pps_config()
919 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4); in intel_dsc_get_pps_config()
921 vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp); in intel_dsc_get_pps_config()
922 vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp); in intel_dsc_get_pps_config()
925 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5); in intel_dsc_get_pps_config()
927 vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp); in intel_dsc_get_pps_config()
928 vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp); in intel_dsc_get_pps_config()
931 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6); in intel_dsc_get_pps_config()
933 vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp); in intel_dsc_get_pps_config()
934 vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
935 vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp); in intel_dsc_get_pps_config()
936 vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp); in intel_dsc_get_pps_config()
939 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7); in intel_dsc_get_pps_config()
941 vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
942 vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
945 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8); in intel_dsc_get_pps_config()
947 vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
948 vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
951 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9); in intel_dsc_get_pps_config()
953 vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK, pps_temp); in intel_dsc_get_pps_config()
956 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10); in intel_dsc_get_pps_config()
958 vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp); in intel_dsc_get_pps_config()
959 vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp); in intel_dsc_get_pps_config()
962 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16); in intel_dsc_get_pps_config()
964 vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp); in intel_dsc_get_pps_config()
968 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17); in intel_dsc_get_pps_config()
970 vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
973 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18); in intel_dsc_get_pps_config()
975 vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
976 vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp); in intel_dsc_get_pps_config()