Lines Matching refs:plane
213 struct intel_vgpu_primary_plane_format *plane) in intel_vgpu_decode_primary_plane() argument
225 plane->enabled = !!(val & DISP_ENABLE); in intel_vgpu_decode_primary_plane()
226 if (!plane->enabled) in intel_vgpu_decode_primary_plane()
230 plane->tiled = val & PLANE_CTL_TILED_MASK; in intel_vgpu_decode_primary_plane()
242 plane->bpp = skl_pixel_formats[fmt].bpp; in intel_vgpu_decode_primary_plane()
243 plane->drm_format = skl_pixel_formats[fmt].drm_format; in intel_vgpu_decode_primary_plane()
245 plane->tiled = val & DISP_TILED; in intel_vgpu_decode_primary_plane()
247 plane->bpp = bdw_pixel_formats[fmt].bpp; in intel_vgpu_decode_primary_plane()
248 plane->drm_format = bdw_pixel_formats[fmt].drm_format; in intel_vgpu_decode_primary_plane()
251 if (!plane->bpp) { in intel_vgpu_decode_primary_plane()
256 plane->hw_format = fmt; in intel_vgpu_decode_primary_plane()
258 plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_primary_plane()
259 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) in intel_vgpu_decode_primary_plane()
262 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); in intel_vgpu_decode_primary_plane()
263 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { in intel_vgpu_decode_primary_plane()
265 plane->base); in intel_vgpu_decode_primary_plane()
269 plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled, in intel_vgpu_decode_primary_plane()
272 _PRI_PLANE_STRIDE_MASK, plane->bpp); in intel_vgpu_decode_primary_plane()
274 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >> in intel_vgpu_decode_primary_plane()
276 plane->width += 1; in intel_vgpu_decode_primary_plane()
277 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & in intel_vgpu_decode_primary_plane()
279 plane->height += 1; /* raw height is one minus the real value */ in intel_vgpu_decode_primary_plane()
282 plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >> in intel_vgpu_decode_primary_plane()
284 plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >> in intel_vgpu_decode_primary_plane()
344 struct intel_vgpu_cursor_plane_format *plane) in intel_vgpu_decode_cursor_plane() argument
358 plane->enabled = (mode != MCURSOR_MODE_DISABLE); in intel_vgpu_decode_cursor_plane()
359 if (!plane->enabled) in intel_vgpu_decode_cursor_plane()
368 plane->mode = mode; in intel_vgpu_decode_cursor_plane()
369 plane->bpp = cursor_pixel_formats[index].bpp; in intel_vgpu_decode_cursor_plane()
370 plane->drm_format = cursor_pixel_formats[index].drm_format; in intel_vgpu_decode_cursor_plane()
371 plane->width = cursor_pixel_formats[index].width; in intel_vgpu_decode_cursor_plane()
372 plane->height = cursor_pixel_formats[index].height; in intel_vgpu_decode_cursor_plane()
382 plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_cursor_plane()
383 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) in intel_vgpu_decode_cursor_plane()
386 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); in intel_vgpu_decode_cursor_plane()
387 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { in intel_vgpu_decode_cursor_plane()
389 plane->base); in intel_vgpu_decode_cursor_plane()
394 plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT; in intel_vgpu_decode_cursor_plane()
395 plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT; in intel_vgpu_decode_cursor_plane()
396 plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT; in intel_vgpu_decode_cursor_plane()
397 plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT; in intel_vgpu_decode_cursor_plane()
399 plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)); in intel_vgpu_decode_cursor_plane()
400 plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)); in intel_vgpu_decode_cursor_plane()