Lines Matching refs:pvr_dev
19 pvr_mips_init(struct pvr_device *pvr_dev) in pvr_mips_init() argument
21 pvr_fw_heap_info_init(pvr_dev, ROGUE_FW_HEAP_MIPS_SHIFT, ROGUE_FW_HEAP_MIPS_RESERVED_SIZE); in pvr_mips_init()
23 return pvr_vm_mips_init(pvr_dev); in pvr_mips_init()
27 pvr_mips_fini(struct pvr_device *pvr_dev) in pvr_mips_fini() argument
29 pvr_vm_mips_fini(pvr_dev); in pvr_mips_fini()
33 pvr_mips_fw_process(struct pvr_device *pvr_dev, const u8 *fw, in pvr_mips_fw_process() argument
37 struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev; in pvr_mips_fw_process()
47 err = pvr_fw_process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw_data_ptr, in pvr_mips_fw_process()
52 boot_code_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_BOOT_CODE); in pvr_mips_fw_process()
53 boot_data_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_BOOT_DATA); in pvr_mips_fw_process()
54 exception_code_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_EXCEPTIONS_CODE); in pvr_mips_fw_process()
66 stack_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_STACK); in pvr_mips_fw_process()
77 boot_data->reg_base = pvr_dev->regs_resource->start; in pvr_mips_fw_process()
97 pvr_mips_wrapper_init(struct pvr_device *pvr_dev) in pvr_mips_wrapper_init() argument
99 struct pvr_fw_mips_data *mips_data = pvr_dev->fw_dev.processor_data.mips_data; in pvr_mips_wrapper_init()
103 int err = PVR_FEATURE_VALUE(pvr_dev, phys_bus_width, &phys_bus_width); in pvr_mips_wrapper_init()
112 pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_CONFIG, in pvr_mips_wrapper_init()
118 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1, in pvr_mips_wrapper_init()
121 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2, in pvr_mips_wrapper_init()
125 if (PVR_HAS_QUIRK(pvr_dev, 63553)) { in pvr_mips_wrapper_init()
132 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1, in pvr_mips_wrapper_init()
134 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2, in pvr_mips_wrapper_init()
140 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1, in pvr_mips_wrapper_init()
143 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2, in pvr_mips_wrapper_init()
147 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1, in pvr_mips_wrapper_init()
150 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2, in pvr_mips_wrapper_init()
155 pvr_cr_write64(pvr_dev, ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG, in pvr_mips_wrapper_init()
159 pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_DEBUG_CONFIG, 0); in pvr_mips_wrapper_init()
167 struct pvr_device *pvr_dev = to_pvr_device(gem_from_pvr_gem(fw_obj->gem)->dev); in pvr_mips_get_fw_addr_with_offset() local
170 return ((fw_obj->fw_addr_offset + offset) & pvr_dev->fw_dev.fw_heap_info.offset_mask) | in pvr_mips_get_fw_addr_with_offset()
175 pvr_mips_irq_pending(struct pvr_device *pvr_dev) in pvr_mips_irq_pending() argument
177 return pvr_cr_read32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS) & in pvr_mips_irq_pending()
182 pvr_mips_irq_clear(struct pvr_device *pvr_dev) in pvr_mips_irq_clear() argument
184 pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, in pvr_mips_irq_clear()