Lines Matching refs:pvr_dev
23 pvr_riscv_wrapper_init(struct pvr_device *pvr_dev) in pvr_riscv_wrapper_init() argument
31 u64 code_addr = pvr_fw_obj_get_gpu_addr(pvr_dev->fw_dev.mem.code_obj); in pvr_riscv_wrapper_init()
32 u64 data_addr = pvr_fw_obj_get_gpu_addr(pvr_dev->fw_dev.mem.data_obj); in pvr_riscv_wrapper_init()
41 pvr_cr_write64(pvr_dev, ROGUE_RISCVFW_REGION_REMAP_CR(BOOTLDR_CODE), in pvr_riscv_wrapper_init()
44 pvr_cr_write64(pvr_dev, ROGUE_RISCVFW_REGION_REMAP_CR(BOOTLDR_DATA), in pvr_riscv_wrapper_init()
49 pvr_cr_write64(pvr_dev, ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG, in pvr_riscv_wrapper_init()
67 pvr_riscv_fw_process(struct pvr_device *pvr_dev, const u8 *fw, in pvr_riscv_fw_process() argument
71 struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev; in pvr_riscv_fw_process()
76 err = pvr_fw_process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw_data_ptr, in pvr_riscv_fw_process()
102 pvr_riscv_init(struct pvr_device *pvr_dev) in pvr_riscv_init() argument
104 pvr_fw_heap_info_init(pvr_dev, ROGUE_FW_HEAP_RISCV_SHIFT, 0); in pvr_riscv_init()
124 pvr_riscv_vm_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj) in pvr_riscv_vm_map() argument
128 return pvr_vm_map(pvr_dev->kernel_vm_ctx, pvr_obj, 0, fw_obj->fw_mm_node.start, in pvr_riscv_vm_map()
133 pvr_riscv_vm_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj) in pvr_riscv_vm_unmap() argument
137 pvr_vm_unmap_obj(pvr_dev->kernel_vm_ctx, pvr_obj, in pvr_riscv_vm_unmap()
142 pvr_riscv_irq_pending(struct pvr_device *pvr_dev) in pvr_riscv_irq_pending() argument
144 return pvr_cr_read32(pvr_dev, ROGUE_CR_IRQ_OS0_EVENT_STATUS) & in pvr_riscv_irq_pending()
149 pvr_riscv_irq_clear(struct pvr_device *pvr_dev) in pvr_riscv_irq_clear() argument
151 pvr_cr_write32(pvr_dev, ROGUE_CR_IRQ_OS0_EVENT_CLEAR, in pvr_riscv_irq_clear()