Lines Matching refs:pvr_dev
20 rogue_axi_ace_list_init(struct pvr_device *pvr_dev) in rogue_axi_ace_list_init() argument
33 pvr_cr_write64(pvr_dev, ROGUE_CR_AXI_ACE_LITE_CONFIGURATION, reg_val); in rogue_axi_ace_list_init()
37 rogue_bif_init(struct pvr_device *pvr_dev) in rogue_bif_init() argument
43 pc_dma_addr = pvr_vm_get_page_table_root_addr(pvr_dev->kernel_vm_ctx); in rogue_bif_init()
50 pvr_cr_write64(pvr_dev, BIF_CAT_BASEX(MMU_CONTEXT_MAPPING_FWPRIV), in rogue_bif_init()
53 if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_RISCV) { in rogue_bif_init()
58 pvr_cr_write64(pvr_dev, FWCORE_MEM_CAT_BASEX(MMU_CONTEXT_MAPPING_FWPRIV), pc_addr); in rogue_bif_init()
63 rogue_slc_init(struct pvr_device *pvr_dev) in rogue_slc_init() argument
76 reg_val = (pvr_cr_read32(pvr_dev, ROGUE_CR_SLC_CTRL_MISC) & in rogue_slc_init()
80 err = PVR_FEATURE_VALUE(pvr_dev, slc_cache_line_size_bits, &slc_cache_line_size_bits); in rogue_slc_init()
88 if (PVR_HAS_QUIRK(pvr_dev, 71242) && !PVR_HAS_FEATURE(pvr_dev, gpu_multicore_support)) in rogue_slc_init()
91 pvr_cr_write32(pvr_dev, ROGUE_CR_SLC_CTRL_MISC, reg_val); in rogue_slc_init()
105 pvr_fw_start(struct pvr_device *pvr_dev) in pvr_fw_start() argument
107 bool has_reset2 = PVR_HAS_FEATURE(pvr_dev, xe_tpu2); in pvr_fw_start()
111 if (PVR_HAS_FEATURE(pvr_dev, pbe2_in_xe)) in pvr_fw_start()
116 if (PVR_HAS_FEATURE(pvr_dev, sys_bus_secure_reset)) { in pvr_fw_start()
121 pvr_cr_write32(pvr_dev, ROGUE_CR_SYS_BUS_SECURE, 0); in pvr_fw_start()
122 (void)pvr_cr_read32(pvr_dev, ROGUE_CR_SYS_BUS_SECURE); /* Fence write */ in pvr_fw_start()
125 if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_RISCV) in pvr_fw_start()
126 pvr_cr_write32(pvr_dev, ROGUE_CR_FWCORE_BOOT, 0); in pvr_fw_start()
129 pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, soft_reset_mask); in pvr_fw_start()
131 pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET2, ROGUE_CR_SOFT_RESET2_MASKFULL); in pvr_fw_start()
134 (void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET); in pvr_fw_start()
136 (void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET2); in pvr_fw_start()
139 pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, in pvr_fw_start()
142 pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET2, 0); in pvr_fw_start()
144 (void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET); in pvr_fw_start()
146 (void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET2); in pvr_fw_start()
149 pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, ROGUE_CR_SOFT_RESET_GARTEN_EN); in pvr_fw_start()
151 pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET2, 0); in pvr_fw_start()
153 (void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET); in pvr_fw_start()
155 (void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET2); in pvr_fw_start()
157 err = rogue_slc_init(pvr_dev); in pvr_fw_start()
162 pvr_dev->fw_dev.defs->wrapper_init(pvr_dev); in pvr_fw_start()
165 rogue_axi_ace_list_init(pvr_dev); in pvr_fw_start()
167 if (pvr_dev->fw_dev.processor_type != PVR_FW_PROCESSOR_TYPE_MIPS) { in pvr_fw_start()
169 rogue_bif_init(pvr_dev); in pvr_fw_start()
175 pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, 0x0); in pvr_fw_start()
176 (void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET); in pvr_fw_start()
181 if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_RISCV) { in pvr_fw_start()
183 pvr_cr_write32(pvr_dev, ROGUE_CR_FWCORE_BOOT, 1); in pvr_fw_start()
191 pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, soft_reset_mask); in pvr_fw_start()
205 pvr_fw_stop(struct pvr_device *pvr_dev) in pvr_fw_stop() argument
220 err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, in pvr_fw_stop()
226 pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC, in pvr_fw_stop()
229 pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC, in pvr_fw_stop()
232 pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, in pvr_fw_stop()
235 pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, in pvr_fw_stop()
240 err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIF_STATUS_MMU, 0, in pvr_fw_stop()
246 err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIFPM_STATUS_MMU, 0, in pvr_fw_stop()
252 if (!PVR_HAS_FEATURE(pvr_dev, xt_top_infrastructure)) { in pvr_fw_stop()
253 err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIF_READS_EXT_STATUS, 0, in pvr_fw_stop()
260 err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIFPM_READS_EXT_STATUS, 0, in pvr_fw_stop()
266 err = pvr_cr_poll_reg64(pvr_dev, ROGUE_CR_SLC_STATUS1, 0, in pvr_fw_stop()
277 err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, in pvr_fw_stop()
288 err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, in pvr_fw_stop()
293 if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_META) { in pvr_fw_stop()
294 err = pvr_meta_cr_read32(pvr_dev, META_CR_TxVECINT_BHALT, ®_value); in pvr_fw_stop()
308 err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, in pvr_fw_stop()
316 if (PVR_HAS_FEATURE(pvr_dev, pbe2_in_xe)) in pvr_fw_stop()
317 pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, in pvr_fw_stop()
320 pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, ROGUE_CR_SOFT_RESET_MASKFULL); in pvr_fw_stop()