Lines Matching refs:control_status
90 u32 control_status; member
172 dtg->control_status |= OVL_DATA_MODE | BLENDER_VIDEO_ALPHA_SEL | in dcss_dtg_init()
291 dtg->control_status |= in dcss_dtg_css_set()
297 dtg->control_status |= DTG_START; in dcss_dtg_enable()
299 dtg->control_status &= ~(CH1_ALPHA_SEL | DEFAULT_FG_ALPHA_MASK); in dcss_dtg_enable()
300 dtg->control_status |= dtg->alpha_cfg; in dcss_dtg_enable()
302 dcss_dtg_write(dtg, dtg->control_status, DCSS_DTG_TC_CONTROL_STATUS); in dcss_dtg_enable()
309 dtg->control_status &= ~DTG_START; in dcss_dtg_shutoff()
311 dcss_writel(dtg->control_status, in dcss_dtg_shutoff()
325 u32 control_status; in dcss_dtg_ch_enable() local
327 control_status = dtg->control_status & ~ch_en_map[ch_num]; in dcss_dtg_ch_enable()
328 control_status |= en ? ch_en_map[ch_num] : 0; in dcss_dtg_ch_enable()
330 control_status &= ~(CH1_ALPHA_SEL | DEFAULT_FG_ALPHA_MASK); in dcss_dtg_ch_enable()
331 control_status |= dtg->alpha_cfg; in dcss_dtg_ch_enable()
333 if (dtg->control_status != control_status) in dcss_dtg_ch_enable()
334 dcss_dtg_write(dtg, control_status, DCSS_DTG_TC_CONTROL_STATUS); in dcss_dtg_ch_enable()
336 dtg->control_status = control_status; in dcss_dtg_ch_enable()