Lines Matching refs:val
93 u32 val; in mcde_display_irq() local
106 val = readl(mcde->regs + MCDE_CRA0); in mcde_display_irq()
107 val &= ~MCDE_CRX0_FLOEN; in mcde_display_irq()
108 writel(val, mcde->regs + MCDE_CRA0); in mcde_display_irq()
199 u32 val; in mcde_configure_extsrc() local
251 val = 0 << MCDE_EXTSRCXCONF_BUF_ID_SHIFT; in mcde_configure_extsrc()
252 val |= 1 << MCDE_EXTSRCXCONF_BUF_NB_SHIFT; in mcde_configure_extsrc()
253 val |= 0 << MCDE_EXTSRCXCONF_PRI_OVLID_SHIFT; in mcde_configure_extsrc()
257 val |= MCDE_EXTSRCXCONF_BPP_ARGB8888 << in mcde_configure_extsrc()
261 val |= MCDE_EXTSRCXCONF_BPP_ARGB8888 << in mcde_configure_extsrc()
263 val |= MCDE_EXTSRCXCONF_BGR; in mcde_configure_extsrc()
266 val |= MCDE_EXTSRCXCONF_BPP_XRGB8888 << in mcde_configure_extsrc()
270 val |= MCDE_EXTSRCXCONF_BPP_XRGB8888 << in mcde_configure_extsrc()
272 val |= MCDE_EXTSRCXCONF_BGR; in mcde_configure_extsrc()
275 val |= MCDE_EXTSRCXCONF_BPP_RGB888 << in mcde_configure_extsrc()
279 val |= MCDE_EXTSRCXCONF_BPP_RGB888 << in mcde_configure_extsrc()
281 val |= MCDE_EXTSRCXCONF_BGR; in mcde_configure_extsrc()
284 val |= MCDE_EXTSRCXCONF_BPP_ARGB4444 << in mcde_configure_extsrc()
288 val |= MCDE_EXTSRCXCONF_BPP_ARGB4444 << in mcde_configure_extsrc()
290 val |= MCDE_EXTSRCXCONF_BGR; in mcde_configure_extsrc()
293 val |= MCDE_EXTSRCXCONF_BPP_RGB444 << in mcde_configure_extsrc()
297 val |= MCDE_EXTSRCXCONF_BPP_RGB444 << in mcde_configure_extsrc()
299 val |= MCDE_EXTSRCXCONF_BGR; in mcde_configure_extsrc()
302 val |= MCDE_EXTSRCXCONF_BPP_IRGB1555 << in mcde_configure_extsrc()
306 val |= MCDE_EXTSRCXCONF_BPP_IRGB1555 << in mcde_configure_extsrc()
308 val |= MCDE_EXTSRCXCONF_BGR; in mcde_configure_extsrc()
311 val |= MCDE_EXTSRCXCONF_BPP_RGB565 << in mcde_configure_extsrc()
315 val |= MCDE_EXTSRCXCONF_BPP_RGB565 << in mcde_configure_extsrc()
317 val |= MCDE_EXTSRCXCONF_BGR; in mcde_configure_extsrc()
320 val |= MCDE_EXTSRCXCONF_BPP_YCBCR422 << in mcde_configure_extsrc()
328 writel(val, mcde->regs + conf); in mcde_configure_extsrc()
331 val = MCDE_EXTSRCXCR_SEL_MOD_SOFTWARE_SEL; in mcde_configure_extsrc()
332 val |= MCDE_EXTSRCXCR_MULTIOVL_CTRL_PRIMARY; in mcde_configure_extsrc()
333 writel(val, mcde->regs + cr); in mcde_configure_extsrc()
344 u32 val; in mcde_configure_overlay() local
404 val = mode->hdisplay << MCDE_OVLXCONF_PPL_SHIFT; in mcde_configure_overlay()
405 val |= mode->vdisplay << MCDE_OVLXCONF_LPF_SHIFT; in mcde_configure_overlay()
407 val |= src << MCDE_OVLXCONF_EXTSRC_ID_SHIFT; in mcde_configure_overlay()
408 writel(val, mcde->regs + conf1); in mcde_configure_overlay()
410 val = MCDE_OVLXCONF2_BP_PER_PIXEL_ALPHA; in mcde_configure_overlay()
411 val |= 0xff << MCDE_OVLXCONF2_ALPHAVALUE_SHIFT; in mcde_configure_overlay()
429 val |= MCDE_OVLXCONF2_OPQ; in mcde_configure_overlay()
462 val |= pixel_fetcher_watermark << MCDE_OVLXCONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT; in mcde_configure_overlay()
463 writel(val, mcde->regs + conf2); in mcde_configure_overlay()
471 val = MCDE_OVLXCR_OVLEN; in mcde_configure_overlay()
472 val |= MCDE_OVLXCR_COLCCTRL_DISABLED; in mcde_configure_overlay()
473 val |= MCDE_OVLXCR_BURSTSIZE_8W << in mcde_configure_overlay()
475 val |= MCDE_OVLXCR_MAXOUTSTANDING_8_REQ << in mcde_configure_overlay()
478 val |= MCDE_OVLXCR_ROTBURSTSIZE_8W << in mcde_configure_overlay()
480 writel(val, mcde->regs + cr); in mcde_configure_overlay()
486 val = ch << MCDE_OVLXCOMP_CH_ID_SHIFT; in mcde_configure_overlay()
487 writel(val, mcde->regs + comp); in mcde_configure_overlay()
494 u32 val; in mcde_configure_channel() local
536 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SOFTWARE in mcde_configure_channel()
540 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE in mcde_configure_channel()
542 val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0 in mcde_configure_channel()
546 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE in mcde_configure_channel()
554 val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER in mcde_configure_channel()
558 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE in mcde_configure_channel()
560 val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0 in mcde_configure_channel()
565 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE in mcde_configure_channel()
567 val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER in mcde_configure_channel()
576 writel(val, mcde->regs + sync); in mcde_configure_channel()
579 val = (mode->hdisplay - 1) << MCDE_CHNLXCONF_PPL_SHIFT; in mcde_configure_channel()
580 val |= (mode->vdisplay - 1) << MCDE_CHNLXCONF_LPF_SHIFT; in mcde_configure_channel()
581 writel(val, mcde->regs + conf); in mcde_configure_channel()
587 val = MCDE_CHNLXSTAT_CHNLBLBCKGND_EN | in mcde_configure_channel()
589 writel(val, mcde->regs + stat); in mcde_configure_channel()
614 val = MCDE_SYNCHCONF_HWREQVEVENT_ACTIVE_VIDEO | in mcde_configure_channel()
621 writel(val, mcde->regs + MCDE_SYNCHCONFA); in mcde_configure_channel()
624 writel(val, mcde->regs + MCDE_SYNCHCONFB); in mcde_configure_channel()
634 u32 val; in mcde_configure_fifo() local
651 val = fifo_wtrmrk << MCDE_CTRLX_FIFOWTRMRK_SHIFT; in mcde_configure_fifo()
663 val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT; in mcde_configure_fifo()
664 val |= MCDE_CTRLX_FORMID_DSI0VID << MCDE_CTRLX_FORMID_SHIFT; in mcde_configure_fifo()
667 val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT; in mcde_configure_fifo()
668 val |= MCDE_CTRLX_FORMID_DSI0CMD << MCDE_CTRLX_FORMID_SHIFT; in mcde_configure_fifo()
671 val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT; in mcde_configure_fifo()
672 val |= MCDE_CTRLX_FORMID_DSI1VID << MCDE_CTRLX_FORMID_SHIFT; in mcde_configure_fifo()
675 val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT; in mcde_configure_fifo()
676 val |= MCDE_CTRLX_FORMID_DSI1CMD << MCDE_CTRLX_FORMID_SHIFT; in mcde_configure_fifo()
679 val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT; in mcde_configure_fifo()
680 val |= MCDE_CTRLX_FORMID_DSI2VID << MCDE_CTRLX_FORMID_SHIFT; in mcde_configure_fifo()
683 val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT; in mcde_configure_fifo()
684 val |= MCDE_CTRLX_FORMID_DSI2CMD << MCDE_CTRLX_FORMID_SHIFT; in mcde_configure_fifo()
687 val |= MCDE_CTRLX_FORMTYPE_DPITV << MCDE_CTRLX_FORMTYPE_SHIFT; in mcde_configure_fifo()
688 val |= MCDE_CTRLX_FORMID_DPIA << MCDE_CTRLX_FORMID_SHIFT; in mcde_configure_fifo()
691 val |= MCDE_CTRLX_FORMTYPE_DPITV << MCDE_CTRLX_FORMTYPE_SHIFT; in mcde_configure_fifo()
692 val |= MCDE_CTRLX_FORMID_DPIB << MCDE_CTRLX_FORMID_SHIFT; in mcde_configure_fifo()
695 writel(val, mcde->regs + ctrl); in mcde_configure_fifo()
698 val = MCDE_CRX0_BLENDEN | in mcde_configure_fifo()
700 writel(val, mcde->regs + cr0); in mcde_configure_fifo()
703 val = readl(mcde->regs + cr1); in mcde_configure_fifo()
726 val &= ~MCDE_CRX1_CDWIN_MASK; in mcde_configure_fifo()
727 val &= ~MCDE_CRX1_OUTBPP_MASK; in mcde_configure_fifo()
730 val |= MCDE_CRX1_CDWIN_24BPP << MCDE_CRX1_CDWIN_SHIFT; in mcde_configure_fifo()
731 val |= MCDE_CRX1_OUTBPP_24BPP << MCDE_CRX1_OUTBPP_SHIFT; in mcde_configure_fifo()
735 val |= MCDE_CRX1_CDWIN_24BPP << MCDE_CRX1_CDWIN_SHIFT; in mcde_configure_fifo()
736 val |= MCDE_CRX1_OUTBPP_24BPP << MCDE_CRX1_OUTBPP_SHIFT; in mcde_configure_fifo()
741 val &= ~MCDE_CRX1_CLKSEL_MASK; in mcde_configure_fifo()
742 val |= MCDE_CRX1_CLKSEL_MCDECLK << MCDE_CRX1_CLKSEL_SHIFT; in mcde_configure_fifo()
744 writel(val, mcde->regs + cr1); in mcde_configure_fifo()
753 u32 val; in mcde_configure_dsi_formatter() local
798 val = MCDE_DSICONF0_CMD8 | MCDE_DSICONF0_DCSVID_NOTGEN; in mcde_configure_dsi_formatter()
800 val |= MCDE_DSICONF0_VID_MODE_VID; in mcde_configure_dsi_formatter()
803 val |= MCDE_DSICONF0_PACKING_RGB888 << in mcde_configure_dsi_formatter()
807 val |= MCDE_DSICONF0_PACKING_RGB666 << in mcde_configure_dsi_formatter()
813 val |= MCDE_DSICONF0_PACKING_RGB666 << in mcde_configure_dsi_formatter()
817 val |= MCDE_DSICONF0_PACKING_RGB565 << in mcde_configure_dsi_formatter()
824 writel(val, mcde->regs + conf0); in mcde_configure_dsi_formatter()
830 val = MIPI_DCS_WRITE_MEMORY_CONTINUE << in mcde_configure_dsi_formatter()
832 val |= MIPI_DCS_WRITE_MEMORY_START << in mcde_configure_dsi_formatter()
834 writel(val, mcde->regs + cmdw); in mcde_configure_dsi_formatter()
846 u32 val; in mcde_enable_fifo() local
863 val = readl(mcde->regs + cr); in mcde_enable_fifo()
864 val |= MCDE_CRX0_FLOEN; in mcde_enable_fifo()
865 writel(val, mcde->regs + cr); in mcde_enable_fifo()
874 u32 val; in mcde_disable_fifo() local
891 val = readl(mcde->regs + cr); in mcde_disable_fifo()
892 val &= ~MCDE_CRX0_FLOEN; in mcde_disable_fifo()
893 writel(val, mcde->regs + cr); in mcde_disable_fifo()
918 u32 val; in mcde_drain_pipe() local
946 val = readl(mcde->regs + ctrl); in mcde_drain_pipe()
947 if (!(val & MCDE_CTRLX_FIFOEMPTY)) { in mcde_drain_pipe()
979 u32 val; in mcde_setup_dpi() local
1002 val = 7 << MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT; in mcde_setup_dpi()
1017 val |= 0 << MCDE_CONF0_OUTMUX0_SHIFT; in mcde_setup_dpi()
1019 val |= 1 << MCDE_CONF0_OUTMUX1_SHIFT; in mcde_setup_dpi()
1021 val |= 0 << MCDE_CONF0_OUTMUX2_SHIFT; in mcde_setup_dpi()
1023 val |= 0 << MCDE_CONF0_OUTMUX3_SHIFT; in mcde_setup_dpi()
1025 val |= 2 << MCDE_CONF0_OUTMUX4_SHIFT; in mcde_setup_dpi()
1027 writel(val, mcde->regs + MCDE_CONF0); in mcde_setup_dpi()
1033 val = (vsw << MCDE_TVBL1_BEL1_SHIFT); in mcde_setup_dpi()
1034 val |= (vfp << MCDE_TVBL1_BSL1_SHIFT); in mcde_setup_dpi()
1035 writel(val, mcde->regs + MCDE_TVBL1A); in mcde_setup_dpi()
1037 writel(val, mcde->regs + MCDE_TVBL2A); in mcde_setup_dpi()
1040 val = (vbp << MCDE_TVDVO_DVO1_SHIFT); in mcde_setup_dpi()
1042 val |= (vbp << MCDE_TVDVO_DVO2_SHIFT); in mcde_setup_dpi()
1043 writel(val, mcde->regs + MCDE_TVDVOA); in mcde_setup_dpi()
1049 val = ((hsw - 1) << MCDE_TVLBALW_LBW_SHIFT); in mcde_setup_dpi()
1050 val |= ((hfp - 1) << MCDE_TVLBALW_ALW_SHIFT); in mcde_setup_dpi()
1051 writel(val, mcde->regs + MCDE_TVLBALWA); in mcde_setup_dpi()
1058 val = 0; in mcde_setup_dpi()
1060 val |= MCDE_LCDTIM1B_IHS; in mcde_setup_dpi()
1062 val |= MCDE_LCDTIM1B_IVS; in mcde_setup_dpi()
1064 val |= MCDE_LCDTIM1B_IOE; in mcde_setup_dpi()
1066 val |= MCDE_LCDTIM1B_IPC; in mcde_setup_dpi()
1067 writel(val, mcde->regs + MCDE_LCDTIM1A); in mcde_setup_dpi()
1081 u32 val; in mcde_setup_dsi() local
1093 val = 7 << MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT; in mcde_setup_dsi()
1101 val |= 3 << MCDE_CONF0_OUTMUX0_SHIFT; in mcde_setup_dsi()
1102 val |= 3 << MCDE_CONF0_OUTMUX1_SHIFT; in mcde_setup_dsi()
1103 val |= 0 << MCDE_CONF0_OUTMUX2_SHIFT; in mcde_setup_dsi()
1104 val |= 4 << MCDE_CONF0_OUTMUX3_SHIFT; in mcde_setup_dsi()
1105 val |= 5 << MCDE_CONF0_OUTMUX4_SHIFT; in mcde_setup_dsi()
1106 writel(val, mcde->regs + MCDE_CONF0); in mcde_setup_dsi()
1166 u32 val; in mcde_display_enable() local
1263 val = MCDE_VSCRC_VSPOL; in mcde_display_enable()
1265 val = 0; in mcde_display_enable()
1266 writel(val, mcde->regs + MCDE_VSCRC0); in mcde_display_enable()
1268 val = readl(mcde->regs + MCDE_CRC); in mcde_display_enable()
1269 val |= MCDE_CRC_SYCEN0; in mcde_display_enable()
1270 writel(val, mcde->regs + MCDE_CRC); in mcde_display_enable()
1293 val = readl(mcde->regs + MCDE_CR); in mcde_display_enable()
1294 val |= MCDE_CR_MCDEEN | MCDE_CR_AUTOCLKG_EN; in mcde_display_enable()
1295 writel(val, mcde->regs + MCDE_CR); in mcde_display_enable()
1450 u32 val; in mcde_display_enable_vblank() local
1453 val = MCDE_PP_VCMPA | in mcde_display_enable_vblank()
1459 writel(val, mcde->regs + MCDE_IMSCPP); in mcde_display_enable_vblank()