Lines Matching refs:cmdq_reg
66 struct cmdq_client_reg cmdq_reg; member
70 struct cmdq_client_reg *cmdq_reg, void __iomem *regs, in mtk_ddp_write() argument
75 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write()
76 cmdq_reg->offset + offset, value); in mtk_ddp_write()
83 struct cmdq_client_reg *cmdq_reg, void __iomem *regs, in mtk_ddp_write_relaxed() argument
88 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write_relaxed()
89 cmdq_reg->offset + offset, value); in mtk_ddp_write_relaxed()
96 struct cmdq_client_reg *cmdq_reg, void __iomem *regs, in mtk_ddp_write_mask() argument
101 cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write_mask()
102 cmdq_reg->offset + offset, value, mask); in mtk_ddp_write_mask()
128 void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, in mtk_dither_set_common() argument
137 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5); in mtk_dither_set_common()
138 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7); in mtk_dither_set_common()
143 cmdq_reg, regs, DISP_REG_DITHER_15); in mtk_dither_set_common()
149 cmdq_reg, regs, DISP_REG_DITHER_16); in mtk_dither_set_common()
150 mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg); in mtk_dither_set_common()
160 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE); in mtk_dither_config()
161 mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, in mtk_dither_config()
163 mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG, in mtk_dither_config()
186 mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg, in mtk_dither_set()
197 mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs, in mtk_dsc_config()
199 mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs, in mtk_dsc_config()
201 mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs, in mtk_dsc_config()
210 mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN); in mtk_dsc_start()
226 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE); in mtk_od_config()
227 mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG); in mtk_od_config()
244 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, in mtk_postmask_config()
246 mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, in mtk_postmask_config()
679 ret = cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0); in mtk_ddp_comp_init()