Lines Matching refs:gpu
30 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, in zap_shader_load_mdt() argument
33 struct device *dev = &gpu->pdev->dev; in zap_shader_load_mdt()
85 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev); in zap_shader_load_mdt()
90 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); in zap_shader_load_mdt()
140 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) { in zap_shader_load_mdt()
176 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) in adreno_zap_shader_load() argument
178 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_zap_shader_load()
179 struct platform_device *pdev = gpu->pdev; in adreno_zap_shader_load()
191 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); in adreno_zap_shader_load()
195 adreno_create_vm(struct msm_gpu *gpu, in adreno_create_vm() argument
198 return adreno_iommu_create_vm(gpu, pdev, 0); in adreno_create_vm()
202 adreno_iommu_create_vm(struct msm_gpu *gpu, in adreno_iommu_create_vm() argument
211 mmu = msm_iommu_gpu_new(&pdev->dev, gpu, quirks); in adreno_iommu_create_vm()
229 vm = msm_gem_vm_create(gpu->dev, mmu, "gpu", start & GENMASK_ULL(48, 0), in adreno_iommu_create_vm()
238 u64 adreno_private_vm_size(struct msm_gpu *gpu) in adreno_private_vm_size() argument
240 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_private_vm_size()
241 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(&gpu->pdev->dev); in adreno_private_vm_size()
266 struct msm_gpu *gpu = &adreno_gpu->base; in adreno_check_and_reenable_stall() local
267 struct msm_drm_private *priv = gpu->dev->dev_private; in adreno_check_and_reenable_stall()
277 !READ_ONCE(gpu->crashstate)) { in adreno_check_and_reenable_stall()
278 struct msm_mmu *mmu = to_msm_vm(gpu->vm)->mmu; in adreno_check_and_reenable_stall()
292 int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, in adreno_fault_handler() argument
296 struct msm_drm_private *priv = gpu->dev->dev_private; in adreno_fault_handler()
297 struct msm_mmu *mmu = to_msm_vm(gpu->vm)->mmu; in adreno_fault_handler()
300 !READ_ONCE(gpu->crashstate); in adreno_fault_handler()
346 timer_delete(&gpu->hangcheck_timer); in adreno_fault_handler()
354 msm_gpu_fault_crashstate_capture(gpu, &fault_info); in adreno_fault_handler()
361 adreno_smmu_has_prr(struct msm_gpu *gpu) in adreno_smmu_has_prr() argument
363 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(&gpu->pdev->dev); in adreno_smmu_has_prr()
367 int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx, in adreno_get_param() argument
370 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_get_param()
371 struct drm_device *drm = gpu->dev; in adreno_get_param()
405 pm_runtime_get_sync(&gpu->pdev->dev); in adreno_get_param()
406 ret = adreno_gpu->funcs->get_timestamp(gpu, value); in adreno_get_param()
407 pm_runtime_put_autosuspend(&gpu->pdev->dev); in adreno_get_param()
413 *value = gpu->nr_rings * NR_SCHED_PRIORITIES; in adreno_get_param()
420 *value = gpu->global_faults + to_msm_vm(vm)->faults; in adreno_get_param()
422 *value = gpu->global_faults; in adreno_get_param()
425 *value = gpu->suspend_count; in adreno_get_param()
428 if (vm == gpu->vm) in adreno_get_param()
433 if (vm == gpu->vm) in adreno_get_param()
453 *value = adreno_smmu_has_prr(gpu); in adreno_get_param()
456 return UERR(EINVAL, drm, "%s: invalid param: %u", gpu->name, param); in adreno_get_param()
460 int adreno_set_param(struct msm_gpu *gpu, struct msm_context *ctx, in adreno_set_param() argument
463 struct drm_device *drm = gpu->dev; in adreno_set_param()
488 mutex_lock(&gpu->lock); in adreno_set_param()
499 mutex_unlock(&gpu->lock); in adreno_set_param()
506 return msm_context_set_sysprof(ctx, gpu, value); in adreno_set_param()
509 if (ctx->vm == gpu->vm) in adreno_set_param()
523 return UERR(EINVAL, drm, "%s: invalid param: %u", gpu->name, param); in adreno_set_param()
636 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, in adreno_fw_create_bo() argument
642 ptr = msm_gem_kernel_new(gpu->dev, fw->size - 4, in adreno_fw_create_bo()
643 MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->vm, &bo, iova); in adreno_fw_create_bo()
655 int adreno_hw_init(struct msm_gpu *gpu) in adreno_hw_init() argument
657 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_hw_init()
660 VERB("%s", gpu->name); in adreno_hw_init()
667 DRM_DEV_ERROR(gpu->dev->dev, "unable to set SMMU aperture: %d\n", ret); in adreno_hw_init()
670 for (int i = 0; i < gpu->nr_rings; i++) { in adreno_hw_init()
671 struct msm_ringbuffer *ring = gpu->rb[i]; in adreno_hw_init()
697 struct msm_gpu *gpu = &adreno_gpu->base; in get_rptr() local
699 return gpu->funcs->get_rptr(gpu, ring); in get_rptr()
702 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu) in adreno_active_ring() argument
704 return gpu->rb[0]; in adreno_active_ring()
707 void adreno_recover(struct msm_gpu *gpu) in adreno_recover() argument
709 struct drm_device *dev = gpu->dev; in adreno_recover()
715 gpu->funcs->pm_suspend(gpu); in adreno_recover()
716 gpu->funcs->pm_resume(gpu); in adreno_recover()
718 ret = msm_gpu_hw_init(gpu); in adreno_recover()
725 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg) in adreno_flush() argument
742 gpu_write(gpu, reg, wptr); in adreno_flush()
745 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in adreno_idle() argument
747 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_idle()
756 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr); in adreno_idle()
761 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) in adreno_gpu_state_get() argument
763 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_gpu_state_get()
766 WARN_ON(!mutex_is_locked(&gpu->lock)); in adreno_gpu_state_get()
772 for (i = 0; i < gpu->nr_rings; i++) { in adreno_gpu_state_get()
775 state->ring[i].fence = gpu->rb[i]->memptrs->fence; in adreno_gpu_state_get()
776 state->ring[i].iova = gpu->rb[i]->iova; in adreno_gpu_state_get()
777 state->ring[i].seqno = gpu->rb[i]->fctx->last_fence; in adreno_gpu_state_get()
778 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); in adreno_gpu_state_get()
779 state->ring[i].wptr = get_wptr(gpu->rb[i]); in adreno_gpu_state_get()
786 if (gpu->rb[i]->start[j]) in adreno_gpu_state_get()
790 state->ring[i].data = kvmemdup(gpu->rb[i]->start, size << 2, GFP_KERNEL); in adreno_gpu_state_get()
816 state->registers[pos++] = gpu_read(gpu, addr); in adreno_gpu_state_get()
939 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, in adreno_show() argument
942 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_show()
991 for (i = 0; i < gpu->nr_rings; i++) { in adreno_show()
1037 void adreno_dump_info(struct msm_gpu *gpu) in adreno_dump_info() argument
1039 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_dump_info()
1046 for (i = 0; i < gpu->nr_rings; i++) { in adreno_dump_info()
1047 struct msm_ringbuffer *ring = gpu->rb[i]; in adreno_dump_info()
1059 void adreno_dump(struct msm_gpu *gpu) in adreno_dump() argument
1061 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_dump()
1068 printk("IO:region %s 00000000 00020000\n", gpu->name); in adreno_dump()
1075 uint32_t val = gpu_read(gpu, addr); in adreno_dump()
1083 struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu); in ring_freewords()
1094 DRM_DEV_ERROR(ring->gpu->dev->dev, in adreno_wait_ring()
1100 struct msm_gpu *gpu) in adreno_get_pwrlevels() argument
1102 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_get_pwrlevels()
1107 gpu->fast_rate = 0; in adreno_get_pwrlevels()
1133 gpu->fast_rate = freq; in adreno_get_pwrlevels()
1136 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); in adreno_get_pwrlevels()
1194 struct msm_gpu *gpu = &adreno_gpu->base; in adreno_gpu_init() local
1203 gpu->allow_relocs = config->info->family < ADRENO_6XX_GEN1; in adreno_gpu_init()
1204 gpu->pdev = pdev; in adreno_gpu_init()
1237 ret = adreno_get_pwrlevels(dev, gpu); in adreno_gpu_init()
1251 struct msm_gpu *gpu = &adreno_gpu->base; in adreno_gpu_cleanup() local
1252 struct msm_drm_private *priv = gpu->dev ? gpu->dev->dev_private : NULL; in adreno_gpu_cleanup()