Lines Matching refs:phys_enc
229 u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc) in dpu_encoder_get_drm_fmt() argument
236 drm_enc = phys_enc->parent; in dpu_encoder_get_drm_fmt()
239 mode = &phys_enc->cached_mode; in dpu_encoder_get_drm_fmt()
252 bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc) in dpu_encoder_needs_periph_flush() argument
260 drm_enc = phys_enc->parent; in dpu_encoder_needs_periph_flush()
264 mode = &phys_enc->cached_mode; in dpu_encoder_needs_periph_flush()
266 return phys_enc->hw_intf->cap->type == INTF_DP && in dpu_encoder_needs_periph_flush()
434 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, in dpu_encoder_helper_report_irq_timeout() argument
438 DRMID(phys_enc->parent), in dpu_encoder_helper_report_irq_timeout()
439 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode), in dpu_encoder_helper_report_irq_timeout()
440 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1, in dpu_encoder_helper_report_irq_timeout()
441 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1, in dpu_encoder_helper_report_irq_timeout()
442 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); in dpu_encoder_helper_report_irq_timeout()
444 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, in dpu_encoder_helper_report_irq_timeout()
460 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, in dpu_encoder_helper_wait_for_irq() argument
475 if (phys_enc->enable_state == DPU_ENC_DISABLED) { in dpu_encoder_helper_wait_for_irq()
477 DRMID(phys_enc->parent), func, in dpu_encoder_helper_wait_for_irq()
484 DRMID(phys_enc->parent), func); in dpu_encoder_helper_wait_for_irq()
489 DRMID(phys_enc->parent), func, in dpu_encoder_helper_wait_for_irq()
490 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0, in dpu_encoder_helper_wait_for_irq()
494 DRMID(phys_enc->parent), in dpu_encoder_helper_wait_for_irq()
499 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx); in dpu_encoder_helper_wait_for_irq()
505 DRMID(phys_enc->parent), func, in dpu_encoder_helper_wait_for_irq()
506 phys_enc->hw_pp->idx - PINGPONG_0, in dpu_encoder_helper_wait_for_irq()
509 func(phys_enc); in dpu_encoder_helper_wait_for_irq()
516 DRMID(phys_enc->parent), func, in dpu_encoder_helper_wait_for_irq()
517 phys_enc->hw_pp->idx - PINGPONG_0, in dpu_encoder_helper_wait_for_irq()
522 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), in dpu_encoder_helper_wait_for_irq()
524 phys_enc->hw_pp->idx - PINGPONG_0, in dpu_encoder_helper_wait_for_irq()
569 struct dpu_encoder_phys *phys_enc, in dpu_encoder_helper_split_config() argument
577 if (!phys_enc->hw_mdptop || !phys_enc->parent) { in dpu_encoder_helper_split_config()
578 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL); in dpu_encoder_helper_split_config()
582 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); in dpu_encoder_helper_split_config()
583 hw_mdptop = phys_enc->hw_mdptop; in dpu_encoder_helper_split_config()
595 if (phys_enc->split_role == ENC_ROLE_SOLO) { in dpu_encoder_helper_split_config()
602 cfg.mode = phys_enc->intf_mode; in dpu_encoder_helper_split_config()
605 if (cfg.en && phys_enc->ops.needs_single_flush && in dpu_encoder_helper_split_config()
606 phys_enc->ops.needs_single_flush(phys_enc)) in dpu_encoder_helper_split_config()
609 if (phys_enc->split_role == ENC_ROLE_MASTER) { in dpu_encoder_helper_split_config()
760 struct dpu_encoder_phys *phys_enc; in _dpu_encoder_update_vsync_source() local
797 phys_enc = dpu_enc->phys_encs[i]; in _dpu_encoder_update_vsync_source()
799 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) in _dpu_encoder_update_vsync_source()
800 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, in _dpu_encoder_update_vsync_source()
1704 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) in dpu_encoder_helper_trigger_start() argument
1708 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_trigger_start()
1711 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); in dpu_encoder_helper_trigger_start()
1742 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) in dpu_encoder_helper_hw_reset() argument
1749 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); in dpu_encoder_helper_hw_reset()
1750 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_hw_reset()
1751 drm_enc = phys_enc->parent; in dpu_encoder_helper_hw_reset()
1765 phys_enc->enable_state = DPU_ENC_ENABLED; in dpu_encoder_helper_hw_reset()
2170 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc) in dpu_encoder_helper_reset_mixers() argument
2177 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; in dpu_encoder_helper_reset_mixers()
2185 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms); in dpu_encoder_helper_reset_mixers()
2187 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state, in dpu_encoder_helper_reset_mixers()
2188 phys_enc->parent->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); in dpu_encoder_helper_reset_mixers()
2252 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) in dpu_encoder_helper_phys_cleanup() argument
2254 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; in dpu_encoder_helper_phys_cleanup()
2259 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); in dpu_encoder_helper_phys_cleanup()
2263 dpu_encoder_helper_reset_mixers(phys_enc); in dpu_encoder_helper_phys_cleanup()
2270 if (phys_enc->hw_wb) { in dpu_encoder_helper_phys_cleanup()
2272 if (phys_enc->hw_wb->ops.bind_pingpong_blk) in dpu_encoder_helper_phys_cleanup()
2273 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, PINGPONG_NONE); in dpu_encoder_helper_phys_cleanup()
2277 ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx); in dpu_encoder_helper_phys_cleanup()
2280 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk) in dpu_encoder_helper_phys_cleanup()
2281 phys_enc->hw_intf->ops.bind_pingpong_blk( in dpu_encoder_helper_phys_cleanup()
2292 if (phys_enc->hw_pp && phys_enc->hw_pp->ops.setup_dither) in dpu_encoder_helper_phys_cleanup()
2293 phys_enc->hw_pp->ops.setup_dither(phys_enc->hw_pp, NULL); in dpu_encoder_helper_phys_cleanup()
2296 dpu_encoder_helper_phys_setup_cwb(phys_enc, false); in dpu_encoder_helper_phys_cleanup()
2299 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) { in dpu_encoder_helper_phys_cleanup()
2300 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, in dpu_encoder_helper_phys_cleanup()
2304 phys_enc->hw_pp->merge_3d->idx); in dpu_encoder_helper_phys_cleanup()
2307 if (phys_enc->hw_cdm) { in dpu_encoder_helper_phys_cleanup()
2308 if (phys_enc->hw_cdm->ops.bind_pingpong_blk && phys_enc->hw_pp) in dpu_encoder_helper_phys_cleanup()
2309 phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm, in dpu_encoder_helper_phys_cleanup()
2313 phys_enc->hw_cdm->idx); in dpu_encoder_helper_phys_cleanup()
2322 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in dpu_encoder_helper_phys_cleanup()
2323 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); in dpu_encoder_helper_phys_cleanup()
2326 if (phys_enc->hw_intf) in dpu_encoder_helper_phys_cleanup()
2327 intf_cfg.intf = phys_enc->hw_intf->idx; in dpu_encoder_helper_phys_cleanup()
2328 if (phys_enc->hw_wb) in dpu_encoder_helper_phys_cleanup()
2329 intf_cfg.wb = phys_enc->hw_wb->idx; in dpu_encoder_helper_phys_cleanup()
2331 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) in dpu_encoder_helper_phys_cleanup()
2332 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; in dpu_encoder_helper_phys_cleanup()
2342 void dpu_encoder_helper_phys_setup_cwb(struct dpu_encoder_phys *phys_enc, in dpu_encoder_helper_phys_setup_cwb() argument
2345 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(phys_enc->parent); in dpu_encoder_helper_phys_setup_cwb()
2355 if (!phys_enc->hw_wb) in dpu_encoder_helper_phys_setup_cwb()
2358 hw_ctl = phys_enc->hw_ctl; in dpu_encoder_helper_phys_setup_cwb()
2360 if (!phys_enc->hw_ctl) { in dpu_encoder_helper_phys_setup_cwb()
2362 phys_enc->hw_wb->idx - WB_0); in dpu_encoder_helper_phys_setup_cwb()
2366 dpu_kms = phys_enc->dpu_kms; in dpu_encoder_helper_phys_setup_cwb()
2369 phys_enc->parent->crtc, in dpu_encoder_helper_phys_setup_cwb()
2410 void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, in dpu_encoder_helper_phys_setup_cdm() argument
2419 if (!phys_enc) in dpu_encoder_helper_phys_setup_cdm()
2422 cdm_cfg = &phys_enc->cdm_cfg; in dpu_encoder_helper_phys_setup_cdm()
2423 hw_pp = phys_enc->hw_pp; in dpu_encoder_helper_phys_setup_cdm()
2424 hw_cdm = phys_enc->hw_cdm; in dpu_encoder_helper_phys_setup_cdm()
2430 DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent), in dpu_encoder_helper_phys_setup_cdm()
2440 cdm_cfg->output_width = phys_enc->cached_mode.hdisplay; in dpu_encoder_helper_phys_setup_cdm()
2441 cdm_cfg->output_height = phys_enc->cached_mode.vdisplay; in dpu_encoder_helper_phys_setup_cdm()
2465 DRMID(phys_enc->parent)); in dpu_encoder_helper_phys_setup_cdm()
2472 DRMID(phys_enc->parent), cdm_cfg->output_width, in dpu_encoder_helper_phys_setup_cdm()
2482 DRMID(phys_enc->parent), ret); in dpu_encoder_helper_phys_setup_cdm()
2900 unsigned int dpu_encoder_helper_get_cwb_mask(struct dpu_encoder_phys *phys_enc) in dpu_encoder_helper_get_cwb_mask() argument
2902 struct drm_encoder *encoder = phys_enc->parent; in dpu_encoder_helper_get_cwb_mask()
2914 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) in dpu_encoder_helper_get_dsc() argument
2916 struct drm_encoder *encoder = phys_enc->parent; in dpu_encoder_helper_get_dsc()
2922 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc, in dpu_encoder_phys_init() argument
2925 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; in dpu_encoder_phys_init()
2926 phys_enc->hw_intf = p->hw_intf; in dpu_encoder_phys_init()
2927 phys_enc->hw_wb = p->hw_wb; in dpu_encoder_phys_init()
2928 phys_enc->parent = p->parent; in dpu_encoder_phys_init()
2929 phys_enc->dpu_kms = p->dpu_kms; in dpu_encoder_phys_init()
2930 phys_enc->split_role = p->split_role; in dpu_encoder_phys_init()
2931 phys_enc->enc_spinlock = p->enc_spinlock; in dpu_encoder_phys_init()
2932 phys_enc->enable_state = DPU_ENC_DISABLED; in dpu_encoder_phys_init()
2934 atomic_set(&phys_enc->pending_kickoff_cnt, 0); in dpu_encoder_phys_init()
2935 atomic_set(&phys_enc->pending_ctlstart_cnt, 0); in dpu_encoder_phys_init()
2937 atomic_set(&phys_enc->vsync_cnt, 0); in dpu_encoder_phys_init()
2938 atomic_set(&phys_enc->underrun_cnt, 0); in dpu_encoder_phys_init()
2940 init_waitqueue_head(&phys_enc->pending_kickoff_wq); in dpu_encoder_phys_init()