Lines Matching refs:dpm_table
405 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table() local
413 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
414 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
416 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
417 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
419 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
421 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; in ci_populate_bapm_parameters_in_dpm_table()
424 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); in ci_populate_bapm_parameters_in_dpm_table()
425 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); in ci_populate_bapm_parameters_in_dpm_table()
427 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
428 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
431 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient); in ci_populate_bapm_parameters_in_dpm_table()
438 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1); in ci_populate_bapm_parameters_in_dpm_table()
439 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2); in ci_populate_bapm_parameters_in_dpm_table()
2511 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2512 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2514 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2515 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2566 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) in ci_get_dpm_level_enable_mask_value() argument
2571 for (i = dpm_table->count; i > 0; i--) { in ci_get_dpm_level_enable_mask_value()
2573 if (dpm_table->dpm_levels[i-1].enabled) in ci_get_dpm_level_enable_mask_value()
2586 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_smc_link_level() local
2589 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { in ci_populate_smc_link_level()
2591 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()
2593 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()
2599 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
2601 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in ci_populate_smc_link_level()
3235 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_graphic_levels() local
3245 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
3247 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3254 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
3260 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3262 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
3282 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_memory_levels() local
3292 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
3293 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3296 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3304 if ((dpm_table->mclk_table.count >= 2) && in ci_populate_all_memory_levels()
3314 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3316 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
3318 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3331 struct ci_single_dpm_table *dpm_table, in ci_reset_single_dpm_table() argument
3336 dpm_table->count = count; in ci_reset_single_dpm_table()
3338 dpm_table->dpm_levels[i].enabled = false; in ci_reset_single_dpm_table()
3341 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table *dpm_table, in ci_setup_pcie_table_entry() argument
3344 dpm_table->dpm_levels[index].value = pcie_gen; in ci_setup_pcie_table_entry()
3345 dpm_table->dpm_levels[index].param1 = pcie_lanes; in ci_setup_pcie_table_entry()
3346 dpm_table->dpm_levels[index].enabled = true; in ci_setup_pcie_table_entry()
3365 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables()
3369 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3373 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3376 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables()
3379 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables()
3382 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, in ci_setup_default_pcie_tables()
3385 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, in ci_setup_default_pcie_tables()
3388 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, in ci_setup_default_pcie_tables()
3392 pi->dpm_table.pcie_speed_table.count = 6; in ci_setup_default_pcie_tables()
3413 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); in ci_setup_default_dpm_tables()
3416 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3419 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
3422 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()
3425 &pi->dpm_table.vddci_table, in ci_setup_default_dpm_tables()
3428 &pi->dpm_table.mvdd_table, in ci_setup_default_dpm_tables()
3431 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3434 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
3436 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3438 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3440 pi->dpm_table.sclk_table.count++; in ci_setup_default_dpm_tables()
3444 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3447 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3449 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3451 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3453 pi->dpm_table.mclk_table.count++; in ci_setup_default_dpm_tables()
3458 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3460 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()
3462 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3464 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()
3468 pi->dpm_table.vddci_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3470 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3472 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3476 pi->dpm_table.mvdd_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3478 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3480 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3577 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, in ci_init_smc_table()
3581 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, in ci_init_smc_table()
3614 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3652 struct ci_single_dpm_table *dpm_table, in ci_trim_single_dpm_states() argument
3657 for (i = 0; i < dpm_table->count; i++) { in ci_trim_single_dpm_states()
3658 if ((dpm_table->dpm_levels[i].value < low_limit) || in ci_trim_single_dpm_states()
3659 (dpm_table->dpm_levels[i].value > high_limit)) in ci_trim_single_dpm_states()
3660 dpm_table->dpm_levels[i].enabled = false; in ci_trim_single_dpm_states()
3662 dpm_table->dpm_levels[i].enabled = true; in ci_trim_single_dpm_states()
3671 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; in ci_trim_pcie_dpm_states()
3713 &pi->dpm_table.sclk_table, in ci_trim_dpm_states()
3718 &pi->dpm_table.mclk_table, in ci_trim_dpm_states()
3808 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3810 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3852 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_and_upload_sclk_mclk_dpm_levels() local
3859 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3862 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
4127 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); in ci_generate_dpm_level_enable_mask()
4129 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); in ci_generate_dpm_level_enable_mask()
4137 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); in ci_generate_dpm_level_enable_mask()
4692 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) in ci_convert_mc_reg_table_to_smc()
4694 pi->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
4733 pi->dpm_table.mclk_table.count, in ci_update_and_upload_mc_reg_table()
5630 SMU7_Discrete_DpmTable *dpm_table; in ci_dpm_init() local
5780 dpm_table = &pi->smc_state_table; in ci_dpm_init()
5784 dpm_table->VRHotGpio = gpio.shift; in ci_dpm_init()
5787 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN; in ci_dpm_init()
5793 dpm_table->AcDcGpio = gpio.shift; in ci_dpm_init()
5796 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN; in ci_dpm_init()