Lines Matching refs:dst_offset
2894 u64 src_offset, dst_offset, dst2_offset; in evergreen_dma_cs_parse() local
2919 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2920 dst_offset <<= 8; in evergreen_dma_cs_parse()
2927 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2928 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_dma_cs_parse()
2938 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2940 dst_offset, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2961 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2962 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2968 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2970 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2988 dst_offset = radeon_get_ib_value(p, idx + 7); in evergreen_dma_cs_parse()
2989 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2999 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3000 dst_offset <<= 8; in evergreen_dma_cs_parse()
3008 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3010 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3020 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3021 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
3027 if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3029 dst_offset + count, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3060 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3061 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
3071 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3073 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3100 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3101 dst_offset <<= 8; in evergreen_dma_cs_parse()
3111 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3113 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3162 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3163 dst_offset <<= 8; in evergreen_dma_cs_parse()
3173 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3175 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3199 dst_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3200 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3210 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3211 dst_offset <<= 8; in evergreen_dma_cs_parse()
3219 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3221 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3249 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3250 dst_offset <<= 8; in evergreen_dma_cs_parse()
3260 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3262 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3287 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3288 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; in evergreen_dma_cs_parse()
3289 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3291 dst_offset, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()