Lines Matching refs:src_offset
2894 u64 src_offset, dst_offset, dst2_offset; in evergreen_dma_cs_parse() local
2959 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2960 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2963 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2965 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
2984 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2985 src_offset <<= 8; in evergreen_dma_cs_parse()
2994 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
2995 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3003 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3005 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3018 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3019 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
3022 if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3024 src_offset + count, radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3064 src_offset = radeon_get_ib_value(p, idx+3); in evergreen_dma_cs_parse()
3065 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in evergreen_dma_cs_parse()
3066 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3068 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3104 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3105 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3106 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3108 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3166 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3167 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3168 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3170 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3195 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3196 src_offset <<= 8; in evergreen_dma_cs_parse()
3205 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3206 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3214 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3216 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3253 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3254 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3255 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3257 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()