Lines Matching refs:dpm
1701 struct si_power_info *pi = rdev->pm.dpm.priv; in si_get_pi()
1775 u32 p_limit1 = rdev->pm.dpm.tdp_limit; in si_update_dte_from_pl2()
1776 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; in si_update_dte_from_pl2()
2066 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) in si_calculate_adjusted_tdp_limits()
2069 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2072 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2073 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); in si_calculate_adjusted_tdp_limits()
2075 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2076 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; in si_calculate_adjusted_tdp_limits()
2077 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) in si_calculate_adjusted_tdp_limits()
2078 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; in si_calculate_adjusted_tdp_limits()
2100 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2113 rdev->pm.dpm.tdp_adjustment, in si_populate_smc_tdp_limits()
2170 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); in si_populate_smc_tdp_limits_2()
2172 …cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_… in si_populate_smc_tdp_limits_2()
2332 if (rdev->pm.dpm.sq_ramping_threshold == 0) in si_populate_sq_ramping_values()
2354 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2473 &rdev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
2610 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; in si_initialize_smc_cac_tables()
2637 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; in si_initialize_smc_cac_tables()
2876 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in si_get_vce_clock_voltage()
2939 if (rdev->pm.dpm.high_pixelclock_count > 1) in si_apply_state_adjust_rules()
2944 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
2945 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in si_apply_state_adjust_rules()
2953 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in si_apply_state_adjust_rules()
2962 if (rdev->pm.dpm.ac_power) in si_apply_state_adjust_rules()
2963 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_apply_state_adjust_rules()
2965 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in si_apply_state_adjust_rules()
2971 if (rdev->pm.dpm.ac_power == false) { in si_apply_state_adjust_rules()
2985 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
2987 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
2989 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3034 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in si_apply_state_adjust_rules()
3035 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in si_apply_state_adjust_rules()
3036 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in si_apply_state_adjust_rules()
3037 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in si_apply_state_adjust_rules()
3091 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3094 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3097 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3100 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in si_apply_state_adjust_rules()
3114 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3340 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in si_dpm_force_performance_level()
3364 rdev->pm.dpm.forced_level = level; in si_dpm_force_performance_level()
3585 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; in si_program_response_times()
3623 if (rdev->pm.dpm.new_active_crtc_count > 0) in si_program_display_gap()
3628 if (rdev->pm.dpm.new_active_crtc_count > 1) in si_program_display_gap()
3638 if ((rdev->pm.dpm.new_active_crtc_count > 0) && in si_program_display_gap()
3639 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { in si_program_display_gap()
3642 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) in si_program_display_gap()
3659 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); in si_program_display_gap()
3912 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_construct_voltage_tables()
3933 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_construct_voltage_tables()
4029 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { in si_populate_smc_voltage_tables()
4091 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { in si_get_std_voltage_value()
4092 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { in si_get_std_voltage_value()
4093 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4096 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4098 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4100 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4102 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4105 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4111 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4113 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4115 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4117 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4120 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4126 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4127 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4379 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_initial_state()
4465 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
4492 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
4633 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; in si_init_smc_table()
4655 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in si_init_smc_table()
4658 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { in si_init_smc_table()
4663 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in si_init_smc_table()
4669 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) in si_init_smc_table()
4672 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { in si_init_smc_table()
4674 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; in si_init_smc_table()
4942 (rdev->pm.dpm.new_active_crtc_count <= 2)) { in si_convert_power_level_to_smc()
5007 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_convert_power_level_to_smc()
5097 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { in si_is_state_ulv_compatible()
5099 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { in si_is_state_ulv_compatible()
5101 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) in si_is_state_ulv_compatible()
5258 if (rdev->pm.dpm.new_active_crtc_count == 0) in si_upload_smc_data()
5262 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { in si_upload_smc_data()
5842 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
5844 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
5846 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
5938 rdev->pm.dpm.thermal.min_temp = low_temp; in si_thermal_set_temperature_range()
5939 rdev->pm.dpm.thermal.max_temp = high_temp; in si_thermal_set_temperature_range()
5978 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
5985 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
5989 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; in si_thermal_setup_fan_table()
5993 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; in si_thermal_setup_fan_table()
5994 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; in si_thermal_setup_fan_table()
5996 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; in si_thermal_setup_fan_table()
5997 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; in si_thermal_setup_fan_table()
6002 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); in si_thermal_setup_fan_table()
6003 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); in si_thermal_setup_fan_table()
6004 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); in si_thermal_setup_fan_table()
6011 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); in si_thermal_setup_fan_table()
6021 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * in si_thermal_setup_fan_table()
6037 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6134 if (rdev->pm.dpm.fan.ucode_fan_control) in si_fan_ctrl_set_mode()
6139 if (rdev->pm.dpm.fan.ucode_fan_control) in si_fan_ctrl_set_mode()
6196 if (rdev->pm.dpm.fan.ucode_fan_control)
6229 if (rdev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_smc_fan_control()
6261 if (rdev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_thermal_controller()
6290 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in si_dpm_enable()
6435 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in si_dpm_disable()
6459 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in si_dpm_pre_set_power_state()
6471 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in si_power_control_set_level()
6663 rdev->pm.dpm.boot_ps = rps; in si_parse_pplib_non_clock_info()
6665 rdev->pm.dpm.uvd_ps = rps; in si_parse_pplib_non_clock_info()
6737 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in si_parse_pplib_clock_info()
6738 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
6739 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
6740 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in si_parse_pplib_clock_info()
6776 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in si_parse_power_table()
6779 if (!rdev->pm.dpm.ps) in si_parse_power_table()
6792 kfree(rdev->pm.dpm.ps); in si_parse_power_table()
6795 rdev->pm.dpm.ps[i].ps_priv = ps; in si_parse_power_table()
6796 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in si_parse_power_table()
6811 &rdev->pm.dpm.ps[i], k, in si_parse_power_table()
6817 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in si_parse_power_table()
6822 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; in si_parse_power_table()
6829 rdev->pm.dpm.vce_states[i].sclk = sclk; in si_parse_power_table()
6830 rdev->pm.dpm.vce_states[i].mclk = mclk; in si_parse_power_table()
6850 rdev->pm.dpm.priv = si_pi; in si_dpm_init()
6896 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in si_dpm_init()
6900 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in si_dpm_init()
6904 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in si_dpm_init()
6905 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in si_dpm_init()
6906 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in si_dpm_init()
6907 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in si_dpm_init()
6908 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in si_dpm_init()
6909 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in si_dpm_init()
6910 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in si_dpm_init()
6911 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in si_dpm_init()
6912 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in si_dpm_init()
6914 if (rdev->pm.dpm.voltage_response_time == 0) in si_dpm_init()
6915 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; in si_dpm_init()
6916 if (rdev->pm.dpm.backbias_response_time == 0) in si_dpm_init()
6917 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; in si_dpm_init()
6994 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in si_dpm_init()
6995 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in si_dpm_init()
6996 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in si_dpm_init()
6997 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in si_dpm_init()
6998 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in si_dpm_init()
6999 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in si_dpm_init()
7000 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in si_dpm_init()
7005 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in si_dpm_init()
7006 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
7007 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
7008 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_dpm_init()
7019 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in si_dpm_fini()
7020 kfree(rdev->pm.dpm.ps[i].ps_priv); in si_dpm_fini()
7022 kfree(rdev->pm.dpm.ps); in si_dpm_fini()
7023 kfree(rdev->pm.dpm.priv); in si_dpm_fini()
7024 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in si_dpm_fini()