Lines Matching refs:dsp_ctrl
877 u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL); in vop2_vp_dsp_lut_is_enabled() local
879 return dsp_ctrl & RK3568_VP_DSP_CTRL__DSP_LUT_EN; in vop2_vp_dsp_lut_is_enabled()
884 u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL); in vop2_vp_dsp_lut_disable() local
886 dsp_ctrl &= ~RK3568_VP_DSP_CTRL__DSP_LUT_EN; in vop2_vp_dsp_lut_disable()
887 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); in vop2_vp_dsp_lut_disable()
892 u32 dsp_ctrl; in vop2_vp_dsp_lut_poll_disabled() local
893 int ret = readx_poll_timeout(vop2_vp_dsp_lut_is_enabled, vp, dsp_ctrl, in vop2_vp_dsp_lut_poll_disabled()
894 !dsp_ctrl, 5, 30 * 1000); in vop2_vp_dsp_lut_poll_disabled()
905 u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL); in vop2_vp_dsp_lut_enable() local
907 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_LUT_EN; in vop2_vp_dsp_lut_enable()
908 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); in vop2_vp_dsp_lut_enable()
913 u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL); in vop2_vp_dsp_lut_update_enable() local
915 dsp_ctrl |= RK3588_VP_DSP_CTRL__GAMMA_UPDATE_EN; in vop2_vp_dsp_lut_update_enable()
916 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); in vop2_vp_dsp_lut_update_enable()
1517 static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl) in vop2_dither_setup() argument
1523 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; in vop2_dither_setup()
1528 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; in vop2_dither_setup()
1529 *dsp_ctrl |= RGB888_TO_RGB666; in vop2_dither_setup()
1533 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; in vop2_dither_setup()
1540 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; in vop2_dither_setup()
1542 *dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL, in vop2_dither_setup()
1626 u32 dsp_ctrl = 0; in vop2_crtc_atomic_enable() local
1685 dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode); in vop2_crtc_atomic_enable()
1688 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP; in vop2_crtc_atomic_enable()
1690 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RG_SWAP; in vop2_crtc_atomic_enable()
1693 dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y; in vop2_crtc_atomic_enable()
1695 vop2_dither_setup(crtc, &dsp_ctrl); in vop2_crtc_atomic_enable()
1715 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE; in vop2_crtc_atomic_enable()
1716 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL; in vop2_crtc_atomic_enable()
1717 dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN; in vop2_crtc_atomic_enable()
1730 dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV; in vop2_crtc_atomic_enable()
1780 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); in vop2_crtc_atomic_enable()