Lines Matching refs:vp
265 unsigned long (*setup_intf_mux)(struct vop2_video_port *vp, int ep_id, u32 polflags);
266 void (*setup_bg_dly)(struct vop2_video_port *vp);
267 void (*setup_overlay)(struct vop2_video_port *vp);
276 const struct vop2_video_port_data *vp; member
423 #define RK3568_VP_LINE_FLAG(vp) (0x70 + (vp) * 0x4) argument
430 #define RK3568_VP_INT_EN(vp) (0xA0 + (vp) * 0x10) argument
431 #define RK3568_VP_INT_CLR(vp) (0xA4 + (vp) * 0x10) argument
432 #define RK3568_VP_INT_STATUS(vp) (0xA8 + (vp) * 0x10) argument
433 #define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10) argument
460 #define RK3576_OVL_CTRL(vp) (0x600 + (vp) * 0x100) argument
461 #define RK3576_OVL_LAYER_SEL(vp) (0x604 + (vp) * 0x100) argument
462 #define RK3576_OVL_MIX0_SRC_COLOR_CTRL(vp) (0x620 + (vp) * 0x100) argument
463 #define RK3576_OVL_MIX0_DST_COLOR_CTRL(vp) (0x624 + (vp) * 0x100) argument
464 #define RK3576_OVL_MIX0_SRC_ALPHA_CTRL(vp) (0x628 + (vp) * 0x100) argument
465 #define RK3576_OVL_MIX0_DST_ALPHA_CTRL(vp) (0x62C + (vp) * 0x100) argument
466 #define RK3576_OVL_MIX1_SRC_COLOR_CTRL(vp) (0x630 + (vp) * 0x100) argument
467 #define RK3576_OVL_MIX1_DST_COLOR_CTRL(vp) (0x634 + (vp) * 0x100) argument
468 #define RK3576_OVL_MIX1_SRC_ALPHA_CTRL(vp) (0x638 + (vp) * 0x100) argument
469 #define RK3576_OVL_MIX1_DST_ALPHA_CTRL(vp) (0x63C + (vp) * 0x100) argument
470 #define RK3576_OVL_MIX2_SRC_COLOR_CTRL(vp) (0x640 + (vp) * 0x100) argument
471 #define RK3576_OVL_MIX2_DST_COLOR_CTRL(vp) (0x644 + (vp) * 0x100) argument
472 #define RK3576_OVL_MIX2_SRC_ALPHA_CTRL(vp) (0x648 + (vp) * 0x100) argument
473 #define RK3576_OVL_MIX2_DST_ALPHA_CTRL(vp) (0x64C + (vp) * 0x100) argument
474 #define RK3576_EXTRA_OVL_SRC_COLOR_CTRL(vp) (0x650 + (vp) * 0x100) argument
475 #define RK3576_EXTRA_OVL_DST_COLOR_CTRL(vp) (0x654 + (vp) * 0x100) argument
476 #define RK3576_EXTRA_OVL_SRC_ALPHA_CTRL(vp) (0x658 + (vp) * 0x100) argument
477 #define RK3576_EXTRA_OVL_DST_ALPHA_CTRL(vp) (0x65C + (vp) * 0x100) argument
478 #define RK3576_OVL_HDR_SRC_COLOR_CTRL(vp) (0x660 + (vp) * 0x100) argument
479 #define RK3576_OVL_HDR_DST_COLOR_CTRL(vp) (0x664 + (vp) * 0x100) argument
480 #define RK3576_OVL_HDR_SRC_ALPHA_CTRL(vp) (0x668 + (vp) * 0x100) argument
481 #define RK3576_OVL_HDR_DST_ALPHA_CTRL(vp) (0x66C + (vp) * 0x100) argument
482 #define RK3576_OVL_BG_MIX_CTRL(vp) (0x670 + (vp) * 0x100) argument
529 #define RK3568_VP_BG_MIX_CTRL(vp) (0x6E0 + (vp) * 4) argument
728 #define RK3568_OVL_CTRL__YUV_MODE(vp) BIT(vp) argument
805 static inline void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v) in vop2_vp_write() argument
807 regmap_write(vp->vop2->map, vp->data->offset + offset, v); in vop2_vp_write()
819 static inline u32 vop2_vp_read(struct vop2_video_port *vp, u32 offset) in vop2_vp_read() argument
823 regmap_read(vp->vop2->map, vp->data->offset + offset, &val); in vop2_vp_read()
857 static inline void vop2_cfg_done(struct vop2_video_port *vp) in vop2_cfg_done() argument
859 struct vop2 *vop2 = vp->vop2; in vop2_cfg_done()
862 val |= BIT(vp->id) | (BIT(vp->id) << 16); in vop2_cfg_done()